| Dan Murphy | bb5a566 | 2016-05-02 15:45:58 -0500 | [diff] [blame] | 1 | /* |
| 2 | * TI DP83867 PHY drivers |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0 |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | #ifndef _DT_BINDINGS_TI_DP83867_H |
| 9 | #define _DT_BINDINGS_TI_DP83867_H |
| 10 | |
| 11 | /* PHY CTRL bits */ |
| 12 | #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 |
| 13 | #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 |
| 14 | #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 |
| 15 | #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 |
| 16 | |
| 17 | /* RGMIIDCTL internal delay for rx and tx */ |
| 18 | #define DP83867_RGMIIDCTL_250_PS 0x0 |
| 19 | #define DP83867_RGMIIDCTL_500_PS 0x1 |
| 20 | #define DP83867_RGMIIDCTL_750_PS 0x2 |
| 21 | #define DP83867_RGMIIDCTL_1_NS 0x3 |
| 22 | #define DP83867_RGMIIDCTL_1_25_NS 0x4 |
| 23 | #define DP83867_RGMIIDCTL_1_50_NS 0x5 |
| 24 | #define DP83867_RGMIIDCTL_1_75_NS 0x6 |
| 25 | #define DP83867_RGMIIDCTL_2_00_NS 0x7 |
| 26 | #define DP83867_RGMIIDCTL_2_25_NS 0x8 |
| 27 | #define DP83867_RGMIIDCTL_2_50_NS 0x9 |
| 28 | #define DP83867_RGMIIDCTL_2_75_NS 0xa |
| 29 | #define DP83867_RGMIIDCTL_3_00_NS 0xb |
| 30 | #define DP83867_RGMIIDCTL_3_25_NS 0xc |
| 31 | #define DP83867_RGMIIDCTL_3_50_NS 0xd |
| 32 | #define DP83867_RGMIIDCTL_3_75_NS 0xe |
| 33 | #define DP83867_RGMIIDCTL_4_00_NS 0xf |
| 34 | |
| 35 | #endif |