blob: 068a9a6ee05042936b8f0fd9712d3e60bdabd3da [file] [log] [blame]
wdenkcc3f8a92004-07-11 19:17:20 +00001/*
2 * (C) Copyright 2004
3 * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkcc3f8a92004-07-11 19:17:20 +00006 */
7
8#define SDRAM_DDR 0 /* is SDR */
9
wdenkcc3f8a92004-07-11 19:17:20 +000010/* Settings for XLB = 132 MHz */
11#define SDRAM_MODE 0x00CD0000
12#define SDRAM_CONTROL 0x504F0000
13#define SDRAM_CONFIG1 0xD2322800
14#define SDRAM_CONFIG2 0x8AD70000