wdenk | 7eaacc5 | 2003-08-29 22:00:43 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Board specific setup info |
| 3 | * |
| 4 | * (C) Copyright 2003 |
| 5 | * Texas Instruments, <www.ti.com> |
| 6 | * Kshitij Gupta <Kshitij@ti.com> |
| 7 | * |
| 8 | * See file CREDITS for list of people who contributed to this |
| 9 | * project. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | */ |
| 26 | |
| 27 | #include <config.h> |
| 28 | #include <version.h> |
| 29 | |
| 30 | #if defined(CONFIG_OMAP1610) |
| 31 | #include <./configs/omap1510.h> |
| 32 | #endif |
| 33 | |
| 34 | |
| 35 | _TEXT_BASE: |
| 36 | .word TEXT_BASE /* sdram load addr from config.mk */ |
| 37 | |
| 38 | .globl platformsetup |
| 39 | platformsetup: |
| 40 | |
| 41 | |
| 42 | /*------------------------------------------------------* |
| 43 | * Set up ARM CLM registers (IDLECT1) * |
| 44 | *------------------------------------------------------*/ |
| 45 | ldr r0, REG_ARM_IDLECT1 |
| 46 | ldr r1, VAL_ARM_IDLECT1 |
| 47 | str r1, [r0] |
| 48 | |
| 49 | /*------------------------------------------------------* |
| 50 | * Set up ARM CLM registers (IDLECT2) * |
| 51 | *------------------------------------------------------*/ |
| 52 | ldr r0, REG_ARM_IDLECT2 |
| 53 | ldr r1, VAL_ARM_IDLECT2 |
| 54 | str r1, [r0] |
| 55 | |
| 56 | /*------------------------------------------------------* |
| 57 | * Set up ARM CLM registers (IDLECT3) * |
| 58 | *------------------------------------------------------*/ |
| 59 | ldr r0, REG_ARM_IDLECT3 |
| 60 | ldr r1, VAL_ARM_IDLECT3 |
| 61 | str r1, [r0] |
| 62 | |
| 63 | |
| 64 | mov r1, #0x01 /* PER_EN bit */ |
| 65 | ldr r0, REG_ARM_RSTCT2 |
| 66 | strh r1, [r0] /* CLKM; Peripheral reset. */ |
| 67 | |
| 68 | /* Set CLKM to Sync-Scalable */ |
| 69 | /* I supposedly need to enable the dsp clock before switching */ |
| 70 | mov r1, #0x0000 |
| 71 | ldr r0, REG_ARM_SYSST |
| 72 | strh r1, [r0] |
| 73 | mov r0, #0x400 |
| 74 | 1: |
| 75 | subs r0, r0, #0x1 /* wait for any bubbles to finish */ |
| 76 | bne 1b |
| 77 | ldr r1, VAL_ARM_CKCTL |
| 78 | ldr r0, REG_ARM_CKCTL |
| 79 | strh r1, [r0] |
| 80 | |
| 81 | /* a few nops to let settle */ |
| 82 | nop |
| 83 | nop |
| 84 | nop |
| 85 | nop |
| 86 | nop |
| 87 | nop |
| 88 | nop |
| 89 | nop |
| 90 | nop |
| 91 | nop |
| 92 | |
| 93 | /* setup DPLL 1 */ |
| 94 | /* Ramp up the clock to 96Mhz */ |
| 95 | ldr r1, VAL_DPLL1_CTL |
| 96 | ldr r0, REG_DPLL1_CTL |
| 97 | strh r1, [r0] |
| 98 | ands r1, r1, #0x10 /* Check if PLL is enabled. */ |
| 99 | beq lock_end /* Do not look for lock if BYPASS selected */ |
| 100 | 2: |
| 101 | ldrh r1, [r0] |
| 102 | ands r1, r1, #0x01 /* Check the LOCK bit.*/ |
| 103 | beq 2b /* loop until bit goes hi. */ |
| 104 | lock_end: |
| 105 | |
| 106 | |
| 107 | /*------------------------------------------------------* |
| 108 | * Turn off the watchdog during init... * |
| 109 | *------------------------------------------------------*/ |
| 110 | ldr r0, REG_WATCHDOG |
| 111 | ldr r1, WATCHDOG_VAL1 |
| 112 | str r1, [r0] |
| 113 | ldr r1, WATCHDOG_VAL2 |
| 114 | str r1, [r0] |
| 115 | ldr r0, REG_WSPRDOG |
| 116 | ldr r1, WSPRDOG_VAL1 |
| 117 | str r1, [r0] |
| 118 | ldr r0, REG_WWPSDOG |
| 119 | |
| 120 | watch1Wait: |
| 121 | ldr r1, [r0] |
| 122 | tst r1, #0x10 |
| 123 | bne watch1Wait |
| 124 | |
| 125 | ldr r0, REG_WSPRDOG |
| 126 | ldr r1, WSPRDOG_VAL2 |
| 127 | str r1, [r0] |
| 128 | ldr r0, REG_WWPSDOG |
| 129 | watch2Wait: |
| 130 | ldr r1, [r0] |
| 131 | tst r1, #0x10 |
| 132 | bne watch2Wait |
| 133 | |
| 134 | |
| 135 | |
| 136 | |
| 137 | /* Set memory timings corresponding to the new clock speed */ |
| 138 | |
| 139 | /* Check execution location to determine current execution location |
| 140 | * and branch to appropriate initialization code. |
| 141 | */ |
| 142 | /* Load physical SDRAM base. */ |
| 143 | mov r0, #0x10000000 |
| 144 | /* Get current execution location. */ |
| 145 | mov r1, pc |
| 146 | /* Compare. */ |
| 147 | cmp r1, r0 |
| 148 | /* Skip over EMIF-fast initialization if running from SDRAM. */ |
| 149 | bge skip_sdram |
| 150 | |
| 151 | /* |
| 152 | * Delay for SDRAM initialization. |
| 153 | */ |
| 154 | mov r3, #0x1800 /* value should be checked */ |
| 155 | 3: |
| 156 | subs r3, r3, #0x1 /* Decrement count */ |
| 157 | bne 3b |
| 158 | |
| 159 | |
| 160 | /* |
| 161 | * Set SDRAM control values. Disable refresh before MRS command. |
| 162 | */ |
| 163 | |
| 164 | /* mobile ddr operation */ |
| 165 | ldr r0, REG_SDRAM_OPERATION |
| 166 | mov r2, #07 |
| 167 | str r2, [r0] |
| 168 | |
| 169 | /* config register */ |
| 170 | ldr r0, REG_SDRAM_CONFIG |
| 171 | ldr r1, SDRAM_CONFIG_VAL |
| 172 | str r1, [r0] |
| 173 | |
| 174 | /* manual command register */ |
| 175 | ldr r0, REG_SDRAM_MANUAL_CMD |
| 176 | /* issue set cke high */ |
| 177 | mov r1, #CMD_SDRAM_CKE_SET_HIGH |
| 178 | str r1, [r0] |
| 179 | /* issue nop */ |
| 180 | mov r1, #CMD_SDRAM_NOP |
| 181 | str r1, [r0] |
| 182 | |
| 183 | mov r2, #0x0100 |
| 184 | waitMDDR1: |
| 185 | subs r2, r2, #1 |
| 186 | bne waitMDDR1 /* delay loop */ |
| 187 | |
| 188 | /* issue precharge */ |
| 189 | mov r1, #CMD_SDRAM_PRECHARGE |
| 190 | str r1, [r0] |
| 191 | |
| 192 | /* issue autorefresh x 2 */ |
| 193 | mov r1, #CMD_SDRAM_AUTOREFRESH |
| 194 | str r1, [r0] |
| 195 | str r1, [r0] |
| 196 | |
| 197 | /* mrs register ddr mobile */ |
| 198 | ldr r0, REG_SDRAM_MRS |
| 199 | mov r1, #0x33 |
| 200 | str r1, [r0] |
| 201 | |
| 202 | /* emrs1 low-power register */ |
| 203 | ldr r0, REG_SDRAM_EMRS1 |
| 204 | /* self refresh on all banks */ |
| 205 | mov r1, #0 |
| 206 | str r1, [r0] |
| 207 | |
| 208 | ldr r0, REG_DLL_URD_CONTROL |
| 209 | ldr r1, DLL_URD_CONTROL_VAL |
| 210 | str r1, [r0] |
| 211 | |
| 212 | ldr r0, REG_DLL_LRD_CONTROL |
| 213 | ldr r1, DLL_LRD_CONTROL_VAL |
| 214 | str r1, [r0] |
| 215 | |
| 216 | ldr r0, REG_DLL_WRT_CONTROL |
| 217 | ldr r1, DLL_WRT_CONTROL_VAL |
| 218 | str r1, [r0] |
| 219 | |
| 220 | /* delay loop */ |
| 221 | mov r2, #0x0100 |
| 222 | waitMDDR2: |
| 223 | subs r2, r2, #1 |
| 224 | bne waitMDDR2 |
| 225 | |
| 226 | /* |
| 227 | * Delay for SDRAM initialization. |
| 228 | */ |
| 229 | mov r3, #0x1800 |
| 230 | 4: |
| 231 | subs r3, r3, #1 /* Decrement count. */ |
| 232 | bne 4b |
| 233 | b common_tc |
| 234 | |
| 235 | skip_sdram: |
| 236 | |
| 237 | ldr r0, REG_SDRAM_CONFIG |
| 238 | ldr r1, SDRAM_CONFIG_VAL |
| 239 | str r1, [r0] |
| 240 | |
| 241 | common_tc: |
| 242 | /* slow interface */ |
| 243 | ldr r1, VAL_TC_EMIFS_CS0_CONFIG |
| 244 | ldr r0, REG_TC_EMIFS_CS0_CONFIG |
| 245 | str r1, [r0] /* Chip Select 0 */ |
| 246 | |
| 247 | ldr r1, VAL_TC_EMIFS_CS1_CONFIG |
| 248 | ldr r0, REG_TC_EMIFS_CS1_CONFIG |
| 249 | str r1, [r0] /* Chip Select 1 */ |
| 250 | ldr r1, VAL_TC_EMIFS_CS3_CONFIG |
| 251 | ldr r0, REG_TC_EMIFS_CS3_CONFIG |
| 252 | str r1, [r0] /* Chip Select 3 */ |
| 253 | /* back to arch calling code */ |
| 254 | mov pc, lr |
| 255 | |
| 256 | /* the literal pools origin */ |
| 257 | .ltorg |
| 258 | |
| 259 | |
| 260 | REG_TC_EMIFS_CONFIG: /* 32 bits */ |
| 261 | .word 0xfffecc0c |
| 262 | REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ |
| 263 | .word 0xfffecc10 |
| 264 | REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ |
| 265 | .word 0xfffecc14 |
| 266 | REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ |
| 267 | .word 0xfffecc18 |
| 268 | REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ |
| 269 | .word 0xfffecc1c |
| 270 | |
| 271 | /* MPU clock/reset/power mode control registers */ |
| 272 | REG_ARM_CKCTL: /* 16 bits */ |
| 273 | .word 0xfffece00 |
| 274 | |
| 275 | REG_ARM_IDLECT3: /* 16 bits */ |
| 276 | .word 0xfffece24 |
| 277 | REG_ARM_IDLECT2: /* 16 bits */ |
| 278 | .word 0xfffece08 |
| 279 | REG_ARM_IDLECT1: /* 16 bits */ |
| 280 | .word 0xfffece04 |
| 281 | |
| 282 | REG_ARM_RSTCT2: /* 16 bits */ |
| 283 | .word 0xfffece14 |
| 284 | REG_ARM_SYSST: /* 16 bits */ |
| 285 | .word 0xfffece18 |
| 286 | /* DPLL control registers */ |
| 287 | REG_DPLL1_CTL: /* 16 bits */ |
| 288 | .word 0xfffecf00 |
| 289 | |
| 290 | /* Watch Dog register */ |
| 291 | /* secure watchdog stop */ |
| 292 | REG_WSPRDOG: |
| 293 | .word 0xfffeb048 |
| 294 | /* watchdog write pending */ |
| 295 | REG_WWPSDOG: |
| 296 | .word 0xfffeb034 |
| 297 | |
| 298 | WSPRDOG_VAL1: |
| 299 | .word 0x0000aaaa |
| 300 | WSPRDOG_VAL2: |
| 301 | .word 0x00005555 |
| 302 | |
| 303 | /* SDRAM config is: auto refresh enabled, 16 bit 4 bank, |
| 304 | counter @8192 rows, 10 ns, 8 burst */ |
| 305 | REG_SDRAM_CONFIG: |
| 306 | .word 0xfffecc20 |
| 307 | |
| 308 | /* Operation register */ |
| 309 | REG_SDRAM_OPERATION: |
| 310 | .word 0xfffecc80 |
| 311 | |
| 312 | /* Manual command register */ |
| 313 | REG_SDRAM_MANUAL_CMD: |
| 314 | .word 0xfffecc84 |
| 315 | |
| 316 | /* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ |
| 317 | REG_SDRAM_MRS: |
| 318 | .word 0xfffecc70 |
| 319 | |
| 320 | /* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ |
| 321 | REG_SDRAM_EMRS1: |
| 322 | .word 0xfffecc78 |
| 323 | |
| 324 | /* WRT DLL register */ |
| 325 | REG_DLL_WRT_CONTROL: |
| 326 | .word 0xfffecc68 |
| 327 | DLL_WRT_CONTROL_VAL: |
| 328 | .word 0x03f00002 |
| 329 | |
| 330 | /* URD DLL register */ |
| 331 | REG_DLL_URD_CONTROL: |
| 332 | .word 0xfffeccc0 |
| 333 | DLL_URD_CONTROL_VAL: |
| 334 | .word 0x00800002 |
| 335 | |
| 336 | /* LRD DLL register */ |
| 337 | REG_DLL_LRD_CONTROL: |
| 338 | .word 0xfffecccc |
| 339 | |
| 340 | REG_WATCHDOG: |
| 341 | .word 0xfffec808 |
| 342 | |
| 343 | /* 96 MHz Samsung Mobile DDR */ |
| 344 | SDRAM_CONFIG_VAL: |
| 345 | .word 0x001200f4 |
| 346 | |
| 347 | DLL_LRD_CONTROL_VAL: |
| 348 | .word 0x00800002 |
| 349 | |
| 350 | VAL_ARM_CKCTL: |
| 351 | .word 0x3000 |
| 352 | VAL_DPLL1_CTL: |
| 353 | .word 0x2830 |
| 354 | |
| 355 | VAL_TC_EMIFS_CS0_CONFIG: |
| 356 | .word 0x002130b0 |
| 357 | VAL_TC_EMIFS_CS1_CONFIG: |
| 358 | .word 0x00001131 |
| 359 | VAL_TC_EMIFS_CS2_CONFIG: |
| 360 | .word 0x000055f0 |
| 361 | VAL_TC_EMIFS_CS3_CONFIG: |
| 362 | .word 0x88011131 |
| 363 | VAL_TC_EMIFF_SDRAM_CONFIG: |
| 364 | .word 0x010290fc |
| 365 | VAL_TC_EMIFF_MRS: |
| 366 | .word 0x00000027 |
| 367 | |
| 368 | VAL_ARM_IDLECT1: |
| 369 | .word 0x00000400 |
| 370 | |
| 371 | VAL_ARM_IDLECT2: |
| 372 | .word 0x00000886 |
| 373 | VAL_ARM_IDLECT3: |
| 374 | .word 0x00000015 |
| 375 | |
| 376 | WATCHDOG_VAL1: |
| 377 | .word 0x000000f5 |
| 378 | WATCHDOG_VAL2: |
| 379 | .word 0x000000a0 |
| 380 | |
| 381 | /* command values */ |
| 382 | .equ CMD_SDRAM_NOP, 0x00000000 |
| 383 | .equ CMD_SDRAM_PRECHARGE, 0x00000001 |
| 384 | .equ CMD_SDRAM_AUTOREFRESH, 0x00000002 |
| 385 | .equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007 |