Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 1 | /* |
| 2 | * board.c |
| 3 | * |
| 4 | * Board functions for TI AM335X based boards |
| 5 | * |
| 6 | * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ |
| 7 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 8 | * SPDX-License-Identifier: GPL-2.0+ |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #include <common.h> |
Lokesh Vutla | 2fe7c79 | 2017-04-26 13:37:08 +0530 | [diff] [blame] | 12 | #include <dm.h> |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 13 | #include <errno.h> |
| 14 | #include <spl.h> |
Lokesh Vutla | abb44e6 | 2016-05-16 11:47:29 +0530 | [diff] [blame] | 15 | #include <serial.h> |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 16 | #include <asm/arch/cpu.h> |
| 17 | #include <asm/arch/hardware.h> |
| 18 | #include <asm/arch/omap.h> |
| 19 | #include <asm/arch/ddr_defs.h> |
| 20 | #include <asm/arch/clock.h> |
Lokesh Vutla | 0d144f5 | 2016-05-16 11:47:26 +0530 | [diff] [blame] | 21 | #include <asm/arch/clk_synthesizer.h> |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 22 | #include <asm/arch/gpio.h> |
| 23 | #include <asm/arch/mmc_host_def.h> |
| 24 | #include <asm/arch/sys_proto.h> |
Steve Kipisz | be9b6f8 | 2013-07-18 15:13:03 -0400 | [diff] [blame] | 25 | #include <asm/arch/mem.h> |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 26 | #include <asm/io.h> |
| 27 | #include <asm/emif.h> |
| 28 | #include <asm/gpio.h> |
Semen Protsenko | a8cb022 | 2017-06-02 18:00:00 +0300 | [diff] [blame] | 29 | #include <asm/omap_common.h> |
Andrew F. Davis | bd24915 | 2016-08-30 14:06:24 -0500 | [diff] [blame] | 30 | #include <asm/omap_sec_common.h> |
Lokesh Vutla | 2fe7c79 | 2017-04-26 13:37:08 +0530 | [diff] [blame] | 31 | #include <asm/omap_mmc.h> |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 32 | #include <i2c.h> |
| 33 | #include <miiphy.h> |
| 34 | #include <cpsw.h> |
Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame] | 35 | #include <power/tps65217.h> |
| 36 | #include <power/tps65910.h> |
Tom Rini | 303bfe8 | 2013-10-01 12:32:04 -0400 | [diff] [blame] | 37 | #include <environment.h> |
| 38 | #include <watchdog.h> |
Tom Rini | 810b581 | 2014-03-28 12:03:38 -0400 | [diff] [blame] | 39 | #include <environment.h> |
Nishanth Menon | 2afa70d | 2016-02-24 12:30:55 -0600 | [diff] [blame] | 40 | #include "../common/board_detect.h" |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 41 | #include "board.h" |
| 42 | |
| 43 | DECLARE_GLOBAL_DATA_PTR; |
| 44 | |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 45 | /* GPIO that controls power to DDR on EVM-SK */ |
Lokesh Vutla | 0d144f5 | 2016-05-16 11:47:26 +0530 | [diff] [blame] | 46 | #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) |
| 47 | #define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7) |
| 48 | #define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18) |
| 49 | #define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4) |
| 50 | #define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10) |
| 51 | #define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7) |
| 52 | #define GPIO_PHY_RESET GPIO_TO_PIN(2, 5) |
Roger Quadros | bcb4ee8 | 2016-08-24 15:35:50 +0300 | [diff] [blame] | 53 | #define GPIO_ETH0_MODE GPIO_TO_PIN(0, 11) |
| 54 | #define GPIO_ETH1_MODE GPIO_TO_PIN(1, 26) |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 55 | |
| 56 | static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; |
| 57 | |
Roger Quadros | bcb4ee8 | 2016-08-24 15:35:50 +0300 | [diff] [blame] | 58 | #define GPIO0_RISINGDETECT (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT) |
| 59 | #define GPIO1_RISINGDETECT (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT) |
| 60 | |
| 61 | #define GPIO0_IRQSTATUS1 (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1) |
| 62 | #define GPIO1_IRQSTATUS1 (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1) |
| 63 | |
| 64 | #define GPIO0_IRQSTATUSRAW (AM33XX_GPIO0_BASE + 0x024) |
| 65 | #define GPIO1_IRQSTATUSRAW (AM33XX_GPIO1_BASE + 0x024) |
| 66 | |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 67 | /* |
| 68 | * Read header information from EEPROM into global structure. |
| 69 | */ |
Lokesh Vutla | 93e0f5b | 2016-10-14 10:35:25 +0530 | [diff] [blame] | 70 | #ifdef CONFIG_TI_I2C_BOARD_DETECT |
| 71 | void do_board_detect(void) |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 72 | { |
Lokesh Vutla | 93e0f5b | 2016-10-14 10:35:25 +0530 | [diff] [blame] | 73 | enable_i2c0_pin_mux(); |
| 74 | i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); |
| 75 | |
Simon Glass | 4df6757 | 2017-05-12 21:09:55 -0600 | [diff] [blame] | 76 | if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, |
| 77 | CONFIG_EEPROM_CHIP_ADDRESS)) |
Lokesh Vutla | 93e0f5b | 2016-10-14 10:35:25 +0530 | [diff] [blame] | 78 | printf("ti_i2c_eeprom_init failed\n"); |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 79 | } |
Lokesh Vutla | 93e0f5b | 2016-10-14 10:35:25 +0530 | [diff] [blame] | 80 | #endif |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 81 | |
Lokesh Vutla | abb44e6 | 2016-05-16 11:47:29 +0530 | [diff] [blame] | 82 | #ifndef CONFIG_DM_SERIAL |
| 83 | struct serial_device *default_serial_console(void) |
| 84 | { |
| 85 | if (board_is_icev2()) |
| 86 | return &eserial4_device; |
| 87 | else |
| 88 | return &eserial1_device; |
| 89 | } |
| 90 | #endif |
| 91 | |
Tom Rini | 8de09df | 2014-04-09 08:25:57 -0400 | [diff] [blame] | 92 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
Peter Korsgaard | eb6cf7b | 2012-10-18 01:21:12 +0000 | [diff] [blame] | 93 | static const struct ddr_data ddr2_data = { |
Tom Rini | 7f50a57 | 2014-07-07 21:40:16 -0400 | [diff] [blame] | 94 | .datardsratio0 = MT47H128M16RT25E_RD_DQS, |
| 95 | .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, |
| 96 | .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, |
Peter Korsgaard | eb6cf7b | 2012-10-18 01:21:12 +0000 | [diff] [blame] | 97 | }; |
| 98 | |
| 99 | static const struct cmd_control ddr2_cmd_ctrl_data = { |
Peter Korsgaard | 3adb827 | 2012-10-18 01:21:13 +0000 | [diff] [blame] | 100 | .cmd0csratio = MT47H128M16RT25E_RATIO, |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 101 | |
Peter Korsgaard | 3adb827 | 2012-10-18 01:21:13 +0000 | [diff] [blame] | 102 | .cmd1csratio = MT47H128M16RT25E_RATIO, |
Peter Korsgaard | eb6cf7b | 2012-10-18 01:21:12 +0000 | [diff] [blame] | 103 | |
Peter Korsgaard | 3adb827 | 2012-10-18 01:21:13 +0000 | [diff] [blame] | 104 | .cmd2csratio = MT47H128M16RT25E_RATIO, |
Peter Korsgaard | eb6cf7b | 2012-10-18 01:21:12 +0000 | [diff] [blame] | 105 | }; |
| 106 | |
| 107 | static const struct emif_regs ddr2_emif_reg_data = { |
Peter Korsgaard | 3adb827 | 2012-10-18 01:21:13 +0000 | [diff] [blame] | 108 | .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, |
| 109 | .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, |
| 110 | .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, |
| 111 | .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, |
| 112 | .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, |
| 113 | .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, |
Peter Korsgaard | eb6cf7b | 2012-10-18 01:21:12 +0000 | [diff] [blame] | 114 | }; |
| 115 | |
Jyri Sarha | 8d2998b | 2016-12-09 12:29:13 +0200 | [diff] [blame] | 116 | static const struct emif_regs ddr2_evm_emif_reg_data = { |
| 117 | .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, |
| 118 | .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, |
| 119 | .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, |
| 120 | .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, |
| 121 | .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, |
| 122 | .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM, |
| 123 | .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, |
| 124 | }; |
| 125 | |
Peter Korsgaard | eb6cf7b | 2012-10-18 01:21:12 +0000 | [diff] [blame] | 126 | static const struct ddr_data ddr3_data = { |
Peter Korsgaard | 3adb827 | 2012-10-18 01:21:13 +0000 | [diff] [blame] | 127 | .datardsratio0 = MT41J128MJT125_RD_DQS, |
| 128 | .datawdsratio0 = MT41J128MJT125_WR_DQS, |
| 129 | .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, |
| 130 | .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, |
Peter Korsgaard | eb6cf7b | 2012-10-18 01:21:12 +0000 | [diff] [blame] | 131 | }; |
| 132 | |
Tom Rini | 385bc75 | 2013-03-21 04:30:02 +0000 | [diff] [blame] | 133 | static const struct ddr_data ddr3_beagleblack_data = { |
| 134 | .datardsratio0 = MT41K256M16HA125E_RD_DQS, |
| 135 | .datawdsratio0 = MT41K256M16HA125E_WR_DQS, |
| 136 | .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, |
| 137 | .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, |
Tom Rini | 385bc75 | 2013-03-21 04:30:02 +0000 | [diff] [blame] | 138 | }; |
| 139 | |
Jeff Lance | 7c03a22 | 2013-01-14 05:32:20 +0000 | [diff] [blame] | 140 | static const struct ddr_data ddr3_evm_data = { |
| 141 | .datardsratio0 = MT41J512M8RH125_RD_DQS, |
| 142 | .datawdsratio0 = MT41J512M8RH125_WR_DQS, |
| 143 | .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, |
| 144 | .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, |
Jeff Lance | 7c03a22 | 2013-01-14 05:32:20 +0000 | [diff] [blame] | 145 | }; |
| 146 | |
Lokesh Vutla | 5837b90 | 2016-05-16 11:47:24 +0530 | [diff] [blame] | 147 | static const struct ddr_data ddr3_icev2_data = { |
| 148 | .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz, |
| 149 | .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz, |
| 150 | .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz, |
| 151 | .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz, |
| 152 | }; |
| 153 | |
Peter Korsgaard | eb6cf7b | 2012-10-18 01:21:12 +0000 | [diff] [blame] | 154 | static const struct cmd_control ddr3_cmd_ctrl_data = { |
Peter Korsgaard | 3adb827 | 2012-10-18 01:21:13 +0000 | [diff] [blame] | 155 | .cmd0csratio = MT41J128MJT125_RATIO, |
Peter Korsgaard | 3adb827 | 2012-10-18 01:21:13 +0000 | [diff] [blame] | 156 | .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, |
Peter Korsgaard | eb6cf7b | 2012-10-18 01:21:12 +0000 | [diff] [blame] | 157 | |
Peter Korsgaard | 3adb827 | 2012-10-18 01:21:13 +0000 | [diff] [blame] | 158 | .cmd1csratio = MT41J128MJT125_RATIO, |
Peter Korsgaard | 3adb827 | 2012-10-18 01:21:13 +0000 | [diff] [blame] | 159 | .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, |
Peter Korsgaard | eb6cf7b | 2012-10-18 01:21:12 +0000 | [diff] [blame] | 160 | |
Peter Korsgaard | 3adb827 | 2012-10-18 01:21:13 +0000 | [diff] [blame] | 161 | .cmd2csratio = MT41J128MJT125_RATIO, |
Peter Korsgaard | 3adb827 | 2012-10-18 01:21:13 +0000 | [diff] [blame] | 162 | .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, |
Peter Korsgaard | eb6cf7b | 2012-10-18 01:21:12 +0000 | [diff] [blame] | 163 | }; |
| 164 | |
Tom Rini | 385bc75 | 2013-03-21 04:30:02 +0000 | [diff] [blame] | 165 | static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { |
| 166 | .cmd0csratio = MT41K256M16HA125E_RATIO, |
Tom Rini | 385bc75 | 2013-03-21 04:30:02 +0000 | [diff] [blame] | 167 | .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, |
| 168 | |
| 169 | .cmd1csratio = MT41K256M16HA125E_RATIO, |
Tom Rini | 385bc75 | 2013-03-21 04:30:02 +0000 | [diff] [blame] | 170 | .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, |
| 171 | |
| 172 | .cmd2csratio = MT41K256M16HA125E_RATIO, |
Tom Rini | 385bc75 | 2013-03-21 04:30:02 +0000 | [diff] [blame] | 173 | .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, |
| 174 | }; |
| 175 | |
Jeff Lance | 7c03a22 | 2013-01-14 05:32:20 +0000 | [diff] [blame] | 176 | static const struct cmd_control ddr3_evm_cmd_ctrl_data = { |
| 177 | .cmd0csratio = MT41J512M8RH125_RATIO, |
Jeff Lance | 7c03a22 | 2013-01-14 05:32:20 +0000 | [diff] [blame] | 178 | .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, |
| 179 | |
| 180 | .cmd1csratio = MT41J512M8RH125_RATIO, |
Jeff Lance | 7c03a22 | 2013-01-14 05:32:20 +0000 | [diff] [blame] | 181 | .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, |
| 182 | |
| 183 | .cmd2csratio = MT41J512M8RH125_RATIO, |
Jeff Lance | 7c03a22 | 2013-01-14 05:32:20 +0000 | [diff] [blame] | 184 | .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, |
| 185 | }; |
| 186 | |
Lokesh Vutla | 5837b90 | 2016-05-16 11:47:24 +0530 | [diff] [blame] | 187 | static const struct cmd_control ddr3_icev2_cmd_ctrl_data = { |
| 188 | .cmd0csratio = MT41J128MJT125_RATIO_400MHz, |
| 189 | .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, |
| 190 | |
| 191 | .cmd1csratio = MT41J128MJT125_RATIO_400MHz, |
| 192 | .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, |
| 193 | |
| 194 | .cmd2csratio = MT41J128MJT125_RATIO_400MHz, |
| 195 | .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, |
| 196 | }; |
| 197 | |
Peter Korsgaard | eb6cf7b | 2012-10-18 01:21:12 +0000 | [diff] [blame] | 198 | static struct emif_regs ddr3_emif_reg_data = { |
Peter Korsgaard | 3adb827 | 2012-10-18 01:21:13 +0000 | [diff] [blame] | 199 | .sdram_config = MT41J128MJT125_EMIF_SDCFG, |
| 200 | .ref_ctrl = MT41J128MJT125_EMIF_SDREF, |
| 201 | .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, |
| 202 | .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, |
| 203 | .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, |
| 204 | .zq_config = MT41J128MJT125_ZQ_CFG, |
Vaibhav Hiremath | c30d57b | 2013-03-14 21:11:16 +0000 | [diff] [blame] | 205 | .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | |
| 206 | PHY_EN_DYN_PWRDN, |
Peter Korsgaard | eb6cf7b | 2012-10-18 01:21:12 +0000 | [diff] [blame] | 207 | }; |
Jeff Lance | 7c03a22 | 2013-01-14 05:32:20 +0000 | [diff] [blame] | 208 | |
Tom Rini | 385bc75 | 2013-03-21 04:30:02 +0000 | [diff] [blame] | 209 | static struct emif_regs ddr3_beagleblack_emif_reg_data = { |
| 210 | .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, |
| 211 | .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, |
| 212 | .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, |
| 213 | .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, |
| 214 | .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, |
Jyri Sarha | 8d2998b | 2016-12-09 12:29:13 +0200 | [diff] [blame] | 215 | .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK, |
Tom Rini | 385bc75 | 2013-03-21 04:30:02 +0000 | [diff] [blame] | 216 | .zq_config = MT41K256M16HA125E_ZQ_CFG, |
| 217 | .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, |
| 218 | }; |
| 219 | |
Jeff Lance | 7c03a22 | 2013-01-14 05:32:20 +0000 | [diff] [blame] | 220 | static struct emif_regs ddr3_evm_emif_reg_data = { |
| 221 | .sdram_config = MT41J512M8RH125_EMIF_SDCFG, |
| 222 | .ref_ctrl = MT41J512M8RH125_EMIF_SDREF, |
| 223 | .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1, |
| 224 | .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2, |
| 225 | .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3, |
Jyri Sarha | 8d2998b | 2016-12-09 12:29:13 +0200 | [diff] [blame] | 226 | .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM, |
Jeff Lance | 7c03a22 | 2013-01-14 05:32:20 +0000 | [diff] [blame] | 227 | .zq_config = MT41J512M8RH125_ZQ_CFG, |
Vaibhav Hiremath | c30d57b | 2013-03-14 21:11:16 +0000 | [diff] [blame] | 228 | .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY | |
| 229 | PHY_EN_DYN_PWRDN, |
Jeff Lance | 7c03a22 | 2013-01-14 05:32:20 +0000 | [diff] [blame] | 230 | }; |
Peter Korsgaard | eb204db | 2013-05-13 08:36:30 +0000 | [diff] [blame] | 231 | |
Lokesh Vutla | 5837b90 | 2016-05-16 11:47:24 +0530 | [diff] [blame] | 232 | static struct emif_regs ddr3_icev2_emif_reg_data = { |
| 233 | .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz, |
| 234 | .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz, |
| 235 | .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz, |
| 236 | .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz, |
| 237 | .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz, |
| 238 | .zq_config = MT41J128MJT125_ZQ_CFG_400MHz, |
| 239 | .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz | |
| 240 | PHY_EN_DYN_PWRDN, |
| 241 | }; |
| 242 | |
Peter Korsgaard | eb204db | 2013-05-13 08:36:30 +0000 | [diff] [blame] | 243 | #ifdef CONFIG_SPL_OS_BOOT |
| 244 | int spl_start_uboot(void) |
| 245 | { |
| 246 | /* break into full u-boot on 'c' */ |
Tom Rini | 810b581 | 2014-03-28 12:03:38 -0400 | [diff] [blame] | 247 | if (serial_tstc() && serial_getc() == 'c') |
| 248 | return 1; |
| 249 | |
| 250 | #ifdef CONFIG_SPL_ENV_SUPPORT |
| 251 | env_init(); |
Simon Glass | 1753957 | 2017-08-03 12:22:07 -0600 | [diff] [blame] | 252 | env_load(); |
Simon Glass | 22c34c2 | 2017-08-03 12:22:13 -0600 | [diff] [blame] | 253 | if (env_get_yesno("boot_os") != 1) |
Tom Rini | 810b581 | 2014-03-28 12:03:38 -0400 | [diff] [blame] | 254 | return 1; |
| 255 | #endif |
| 256 | |
| 257 | return 0; |
Peter Korsgaard | eb204db | 2013-05-13 08:36:30 +0000 | [diff] [blame] | 258 | } |
| 259 | #endif |
| 260 | |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 261 | const struct dpll_params *get_dpll_ddr_params(void) |
Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame] | 262 | { |
Lokesh Vutla | 6302e53 | 2017-05-05 12:59:10 +0530 | [diff] [blame] | 263 | int ind = get_sys_clk_index(); |
| 264 | |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 265 | if (board_is_evm_sk()) |
Lokesh Vutla | 6302e53 | 2017-05-05 12:59:10 +0530 | [diff] [blame] | 266 | return &dpll_ddr3_303MHz[ind]; |
Jason Kridner | b56b5b3 | 2018-03-07 05:40:41 -0500 | [diff] [blame] | 267 | else if (board_is_pb() || board_is_bone_lt() || board_is_icev2()) |
Lokesh Vutla | 6302e53 | 2017-05-05 12:59:10 +0530 | [diff] [blame] | 268 | return &dpll_ddr3_400MHz[ind]; |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 269 | else if (board_is_evm_15_or_later()) |
Lokesh Vutla | 6302e53 | 2017-05-05 12:59:10 +0530 | [diff] [blame] | 270 | return &dpll_ddr3_303MHz[ind]; |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 271 | else |
Lokesh Vutla | 6302e53 | 2017-05-05 12:59:10 +0530 | [diff] [blame] | 272 | return &dpll_ddr2_266MHz[ind]; |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 273 | } |
Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame] | 274 | |
Lokesh Vutla | 6302e53 | 2017-05-05 12:59:10 +0530 | [diff] [blame] | 275 | static u8 bone_not_connected_to_ac_power(void) |
| 276 | { |
| 277 | if (board_is_bone()) { |
| 278 | uchar pmic_status_reg; |
| 279 | if (tps65217_reg_read(TPS65217_STATUS, |
| 280 | &pmic_status_reg)) |
| 281 | return 1; |
| 282 | if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { |
| 283 | puts("No AC power, switching to default OPP\n"); |
| 284 | return 1; |
| 285 | } |
| 286 | } |
| 287 | return 0; |
| 288 | } |
| 289 | |
| 290 | const struct dpll_params *get_dpll_mpu_params(void) |
| 291 | { |
| 292 | int ind = get_sys_clk_index(); |
| 293 | int freq = am335x_get_efuse_mpu_max_freq(cdev); |
| 294 | |
| 295 | if (bone_not_connected_to_ac_power()) |
| 296 | freq = MPUPLL_M_600; |
| 297 | |
Jason Kridner | b56b5b3 | 2018-03-07 05:40:41 -0500 | [diff] [blame] | 298 | if (board_is_pb() || board_is_bone_lt()) |
Lokesh Vutla | 6302e53 | 2017-05-05 12:59:10 +0530 | [diff] [blame] | 299 | freq = MPUPLL_M_1000; |
| 300 | |
| 301 | switch (freq) { |
| 302 | case MPUPLL_M_1000: |
| 303 | return &dpll_mpu_opp[ind][5]; |
| 304 | case MPUPLL_M_800: |
| 305 | return &dpll_mpu_opp[ind][4]; |
| 306 | case MPUPLL_M_720: |
| 307 | return &dpll_mpu_opp[ind][3]; |
| 308 | case MPUPLL_M_600: |
| 309 | return &dpll_mpu_opp[ind][2]; |
| 310 | case MPUPLL_M_500: |
| 311 | return &dpll_mpu_opp100; |
| 312 | case MPUPLL_M_300: |
| 313 | return &dpll_mpu_opp[ind][0]; |
| 314 | } |
| 315 | |
| 316 | return &dpll_mpu_opp[ind][0]; |
| 317 | } |
| 318 | |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 319 | static void scale_vcores_bone(int freq) |
| 320 | { |
| 321 | int usb_cur_lim, mpu_vdd; |
Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame] | 322 | |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 323 | /* |
| 324 | * Only perform PMIC configurations if board rev > A1 |
| 325 | * on Beaglebone White |
| 326 | */ |
| 327 | if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4)) |
| 328 | return; |
Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame] | 329 | |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 330 | if (i2c_probe(TPS65217_CHIP_PM)) |
| 331 | return; |
Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame] | 332 | |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 333 | /* |
| 334 | * On Beaglebone White we need to ensure we have AC power |
| 335 | * before increasing the frequency. |
| 336 | */ |
Lokesh Vutla | 6302e53 | 2017-05-05 12:59:10 +0530 | [diff] [blame] | 337 | if (bone_not_connected_to_ac_power()) |
| 338 | freq = MPUPLL_M_600; |
Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame] | 339 | |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 340 | /* |
| 341 | * Override what we have detected since we know if we have |
| 342 | * a Beaglebone Black it supports 1GHz. |
| 343 | */ |
Jason Kridner | b56b5b3 | 2018-03-07 05:40:41 -0500 | [diff] [blame] | 344 | if (board_is_pb() || board_is_bone_lt()) |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 345 | freq = MPUPLL_M_1000; |
Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame] | 346 | |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 347 | switch (freq) { |
| 348 | case MPUPLL_M_1000: |
| 349 | mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; |
| 350 | usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; |
| 351 | break; |
| 352 | case MPUPLL_M_800: |
| 353 | mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; |
Lokesh Vutla | e29609a | 2017-06-10 13:22:56 +0530 | [diff] [blame] | 354 | usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 355 | break; |
| 356 | case MPUPLL_M_720: |
| 357 | mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV; |
Lokesh Vutla | e29609a | 2017-06-10 13:22:56 +0530 | [diff] [blame] | 358 | usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 359 | break; |
| 360 | case MPUPLL_M_600: |
| 361 | case MPUPLL_M_500: |
| 362 | case MPUPLL_M_300: |
Lokesh Vutla | e29609a | 2017-06-10 13:22:56 +0530 | [diff] [blame] | 363 | default: |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 364 | mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV; |
| 365 | usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; |
| 366 | break; |
| 367 | } |
Steve Kipisz | 5adac35 | 2013-08-14 10:51:31 -0400 | [diff] [blame] | 368 | |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 369 | if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, |
| 370 | TPS65217_POWER_PATH, |
| 371 | usb_cur_lim, |
| 372 | TPS65217_USB_INPUT_CUR_LIMIT_MASK)) |
| 373 | puts("tps65217_reg_write failure\n"); |
Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame] | 374 | |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 375 | /* Set DCDC3 (CORE) voltage to 1.10V */ |
| 376 | if (tps65217_voltage_update(TPS65217_DEFDCDC3, |
| 377 | TPS65217_DCDC_VOLT_SEL_1100MV)) { |
| 378 | puts("tps65217_voltage_update failure\n"); |
| 379 | return; |
| 380 | } |
Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame] | 381 | |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 382 | /* Set DCDC2 (MPU) voltage */ |
| 383 | if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { |
| 384 | puts("tps65217_voltage_update failure\n"); |
| 385 | return; |
| 386 | } |
Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame] | 387 | |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 388 | /* |
| 389 | * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. |
| 390 | * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. |
| 391 | */ |
| 392 | if (board_is_bone()) { |
Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame] | 393 | if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 394 | TPS65217_DEFLS1, |
Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame] | 395 | TPS65217_LDO_VOLTAGE_OUT_3_3, |
| 396 | TPS65217_LDO_MASK)) |
| 397 | puts("tps65217_reg_write failure\n"); |
| 398 | } else { |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 399 | if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, |
| 400 | TPS65217_DEFLS1, |
| 401 | TPS65217_LDO_VOLTAGE_OUT_1_8, |
| 402 | TPS65217_LDO_MASK)) |
| 403 | puts("tps65217_reg_write failure\n"); |
| 404 | } |
Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame] | 405 | |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 406 | if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, |
| 407 | TPS65217_DEFLS2, |
| 408 | TPS65217_LDO_VOLTAGE_OUT_3_3, |
| 409 | TPS65217_LDO_MASK)) |
| 410 | puts("tps65217_reg_write failure\n"); |
| 411 | } |
Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame] | 412 | |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 413 | void scale_vcores_generic(int freq) |
| 414 | { |
| 415 | int sil_rev, mpu_vdd; |
Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame] | 416 | |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 417 | /* |
| 418 | * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all |
| 419 | * MPU frequencies we support we use a CORE voltage of |
| 420 | * 1.10V. For MPU voltage we need to switch based on |
| 421 | * the frequency we are running at. |
| 422 | */ |
| 423 | if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) |
| 424 | return; |
Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame] | 425 | |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 426 | /* |
| 427 | * Depending on MPU clock and PG we will need a different |
| 428 | * VDD to drive at that speed. |
| 429 | */ |
| 430 | sil_rev = readl(&cdev->deviceid) >> 28; |
| 431 | mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq); |
Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame] | 432 | |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 433 | /* Tell the TPS65910 to use i2c */ |
| 434 | tps65910_set_i2c_control(); |
Steve Kipisz | 5adac35 | 2013-08-14 10:51:31 -0400 | [diff] [blame] | 435 | |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 436 | /* First update MPU voltage. */ |
| 437 | if (tps65910_voltage_update(MPU, mpu_vdd)) |
| 438 | return; |
Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame] | 439 | |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 440 | /* Second, update the CORE voltage. */ |
| 441 | if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0)) |
| 442 | return; |
| 443 | |
Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame] | 444 | } |
| 445 | |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 446 | void gpi2c_init(void) |
Lokesh Vutla | 89a83bf | 2013-07-30 10:48:52 +0530 | [diff] [blame] | 447 | { |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 448 | /* When needed to be invoked prior to BSS initialization */ |
| 449 | static bool first_time = true; |
| 450 | |
| 451 | if (first_time) { |
| 452 | enable_i2c0_pin_mux(); |
| 453 | i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, |
| 454 | CONFIG_SYS_OMAP24_I2C_SLAVE); |
| 455 | first_time = false; |
| 456 | } |
| 457 | } |
| 458 | |
| 459 | void scale_vcores(void) |
| 460 | { |
| 461 | int freq; |
| 462 | |
| 463 | gpi2c_init(); |
| 464 | freq = am335x_get_efuse_mpu_max_freq(cdev); |
| 465 | |
Lokesh Vutla | e29609a | 2017-06-10 13:22:56 +0530 | [diff] [blame] | 466 | if (board_is_beaglebonex()) |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 467 | scale_vcores_bone(freq); |
Lokesh Vutla | 89a83bf | 2013-07-30 10:48:52 +0530 | [diff] [blame] | 468 | else |
Lokesh Vutla | 98f9d22 | 2017-05-05 12:59:09 +0530 | [diff] [blame] | 469 | scale_vcores_generic(freq); |
Lokesh Vutla | 89a83bf | 2013-07-30 10:48:52 +0530 | [diff] [blame] | 470 | } |
| 471 | |
Heiko Schocher | b21f2ac | 2013-07-30 10:48:54 +0530 | [diff] [blame] | 472 | void set_uart_mux_conf(void) |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 473 | { |
Tom Rini | 986d755 | 2014-08-01 09:53:24 -0400 | [diff] [blame] | 474 | #if CONFIG_CONS_INDEX == 1 |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 475 | enable_uart0_pin_mux(); |
Tom Rini | 986d755 | 2014-08-01 09:53:24 -0400 | [diff] [blame] | 476 | #elif CONFIG_CONS_INDEX == 2 |
Andrew Bradford | 65c51ff | 2012-10-25 08:21:30 -0400 | [diff] [blame] | 477 | enable_uart1_pin_mux(); |
Tom Rini | 986d755 | 2014-08-01 09:53:24 -0400 | [diff] [blame] | 478 | #elif CONFIG_CONS_INDEX == 3 |
Andrew Bradford | 65c51ff | 2012-10-25 08:21:30 -0400 | [diff] [blame] | 479 | enable_uart2_pin_mux(); |
Tom Rini | 986d755 | 2014-08-01 09:53:24 -0400 | [diff] [blame] | 480 | #elif CONFIG_CONS_INDEX == 4 |
Andrew Bradford | 65c51ff | 2012-10-25 08:21:30 -0400 | [diff] [blame] | 481 | enable_uart3_pin_mux(); |
Tom Rini | 986d755 | 2014-08-01 09:53:24 -0400 | [diff] [blame] | 482 | #elif CONFIG_CONS_INDEX == 5 |
Andrew Bradford | 65c51ff | 2012-10-25 08:21:30 -0400 | [diff] [blame] | 483 | enable_uart4_pin_mux(); |
Tom Rini | 986d755 | 2014-08-01 09:53:24 -0400 | [diff] [blame] | 484 | #elif CONFIG_CONS_INDEX == 6 |
Andrew Bradford | 65c51ff | 2012-10-25 08:21:30 -0400 | [diff] [blame] | 485 | enable_uart5_pin_mux(); |
Tom Rini | 986d755 | 2014-08-01 09:53:24 -0400 | [diff] [blame] | 486 | #endif |
Heiko Schocher | b21f2ac | 2013-07-30 10:48:54 +0530 | [diff] [blame] | 487 | } |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 488 | |
Heiko Schocher | b21f2ac | 2013-07-30 10:48:54 +0530 | [diff] [blame] | 489 | void set_mux_conf_regs(void) |
| 490 | { |
Nishanth Menon | 2afa70d | 2016-02-24 12:30:55 -0600 | [diff] [blame] | 491 | enable_board_pin_mux(); |
Heiko Schocher | b21f2ac | 2013-07-30 10:48:54 +0530 | [diff] [blame] | 492 | } |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 493 | |
Lokesh Vutla | 303b267 | 2013-12-10 15:02:21 +0530 | [diff] [blame] | 494 | const struct ctrl_ioregs ioregs_evmsk = { |
| 495 | .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, |
| 496 | .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, |
| 497 | .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, |
| 498 | .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, |
| 499 | .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, |
| 500 | }; |
| 501 | |
| 502 | const struct ctrl_ioregs ioregs_bonelt = { |
| 503 | .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| 504 | .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| 505 | .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| 506 | .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| 507 | .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| 508 | }; |
| 509 | |
| 510 | const struct ctrl_ioregs ioregs_evm15 = { |
| 511 | .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE, |
| 512 | .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE, |
| 513 | .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE, |
| 514 | .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE, |
| 515 | .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE, |
| 516 | }; |
| 517 | |
| 518 | const struct ctrl_ioregs ioregs = { |
| 519 | .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, |
| 520 | .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, |
| 521 | .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, |
| 522 | .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, |
| 523 | .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, |
| 524 | }; |
| 525 | |
Heiko Schocher | b21f2ac | 2013-07-30 10:48:54 +0530 | [diff] [blame] | 526 | void sdram_init(void) |
| 527 | { |
Nishanth Menon | 2afa70d | 2016-02-24 12:30:55 -0600 | [diff] [blame] | 528 | if (board_is_evm_sk()) { |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 529 | /* |
| 530 | * EVM SK 1.2A and later use gpio0_7 to enable DDR3. |
| 531 | * This is safe enough to do on older revs. |
| 532 | */ |
| 533 | gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); |
| 534 | gpio_direction_output(GPIO_DDR_VTT_EN, 1); |
| 535 | } |
| 536 | |
Lokesh Vutla | 5837b90 | 2016-05-16 11:47:24 +0530 | [diff] [blame] | 537 | if (board_is_icev2()) { |
| 538 | gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en"); |
| 539 | gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1); |
| 540 | } |
| 541 | |
Nishanth Menon | 2afa70d | 2016-02-24 12:30:55 -0600 | [diff] [blame] | 542 | if (board_is_evm_sk()) |
Lokesh Vutla | 303b267 | 2013-12-10 15:02:21 +0530 | [diff] [blame] | 543 | config_ddr(303, &ioregs_evmsk, &ddr3_data, |
Matt Porter | 65991ec | 2013-03-15 10:07:03 +0000 | [diff] [blame] | 544 | &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); |
Jason Kridner | b56b5b3 | 2018-03-07 05:40:41 -0500 | [diff] [blame] | 545 | else if (board_is_pb() || board_is_bone_lt()) |
Lokesh Vutla | 303b267 | 2013-12-10 15:02:21 +0530 | [diff] [blame] | 546 | config_ddr(400, &ioregs_bonelt, |
Tom Rini | 385bc75 | 2013-03-21 04:30:02 +0000 | [diff] [blame] | 547 | &ddr3_beagleblack_data, |
| 548 | &ddr3_beagleblack_cmd_ctrl_data, |
| 549 | &ddr3_beagleblack_emif_reg_data, 0); |
Nishanth Menon | 2afa70d | 2016-02-24 12:30:55 -0600 | [diff] [blame] | 550 | else if (board_is_evm_15_or_later()) |
Lokesh Vutla | 303b267 | 2013-12-10 15:02:21 +0530 | [diff] [blame] | 551 | config_ddr(303, &ioregs_evm15, &ddr3_evm_data, |
Matt Porter | 65991ec | 2013-03-15 10:07:03 +0000 | [diff] [blame] | 552 | &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); |
Lokesh Vutla | 5837b90 | 2016-05-16 11:47:24 +0530 | [diff] [blame] | 553 | else if (board_is_icev2()) |
| 554 | config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data, |
| 555 | &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data, |
| 556 | 0); |
Jyri Sarha | 8d2998b | 2016-12-09 12:29:13 +0200 | [diff] [blame] | 557 | else if (board_is_gp_evm()) |
| 558 | config_ddr(266, &ioregs, &ddr2_data, |
| 559 | &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0); |
Peter Korsgaard | eb6cf7b | 2012-10-18 01:21:12 +0000 | [diff] [blame] | 560 | else |
Lokesh Vutla | 303b267 | 2013-12-10 15:02:21 +0530 | [diff] [blame] | 561 | config_ddr(266, &ioregs, &ddr2_data, |
Matt Porter | 65991ec | 2013-03-15 10:07:03 +0000 | [diff] [blame] | 562 | &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 563 | } |
Heiko Schocher | b21f2ac | 2013-07-30 10:48:54 +0530 | [diff] [blame] | 564 | #endif |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 565 | |
Alex Kiernan | 20bba2e | 2018-04-01 09:22:37 +0000 | [diff] [blame] | 566 | #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \ |
| 567 | (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))) |
Roger Quadros | bcb4ee8 | 2016-08-24 15:35:50 +0300 | [diff] [blame] | 568 | static void request_and_set_gpio(int gpio, char *name, int val) |
Lokesh Vutla | 0d144f5 | 2016-05-16 11:47:26 +0530 | [diff] [blame] | 569 | { |
| 570 | int ret; |
| 571 | |
| 572 | ret = gpio_request(gpio, name); |
| 573 | if (ret < 0) { |
| 574 | printf("%s: Unable to request %s\n", __func__, name); |
| 575 | return; |
| 576 | } |
| 577 | |
| 578 | ret = gpio_direction_output(gpio, 0); |
| 579 | if (ret < 0) { |
| 580 | printf("%s: Unable to set %s as output\n", __func__, name); |
| 581 | goto err_free_gpio; |
| 582 | } |
| 583 | |
Roger Quadros | bcb4ee8 | 2016-08-24 15:35:50 +0300 | [diff] [blame] | 584 | gpio_set_value(gpio, val); |
Lokesh Vutla | 0d144f5 | 2016-05-16 11:47:26 +0530 | [diff] [blame] | 585 | |
| 586 | return; |
| 587 | |
| 588 | err_free_gpio: |
| 589 | gpio_free(gpio); |
| 590 | } |
| 591 | |
Roger Quadros | bcb4ee8 | 2016-08-24 15:35:50 +0300 | [diff] [blame] | 592 | #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1); |
| 593 | #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0); |
Lokesh Vutla | 0d144f5 | 2016-05-16 11:47:26 +0530 | [diff] [blame] | 594 | |
| 595 | /** |
| 596 | * RMII mode on ICEv2 board needs 50MHz clock. Given the clock |
| 597 | * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle |
| 598 | * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to |
| 599 | * give 50MHz output for Eth0 and 1. |
| 600 | */ |
| 601 | static struct clk_synth cdce913_data = { |
| 602 | .id = 0x81, |
| 603 | .capacitor = 0x90, |
| 604 | .mux = 0x6d, |
| 605 | .pdiv2 = 0x2, |
| 606 | .pdiv3 = 0x2, |
| 607 | }; |
| 608 | #endif |
| 609 | |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 610 | /* |
| 611 | * Basic board specific setup. Pinmux has been handled already. |
| 612 | */ |
| 613 | int board_init(void) |
| 614 | { |
Tom Rini | 303bfe8 | 2013-10-01 12:32:04 -0400 | [diff] [blame] | 615 | #if defined(CONFIG_HW_WATCHDOG) |
| 616 | hw_watchdog_init(); |
| 617 | #endif |
| 618 | |
Tom Rini | f3b6a1d | 2013-08-09 11:22:13 -0400 | [diff] [blame] | 619 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
pekon gupta | 53b4b32 | 2013-11-18 19:03:02 +0530 | [diff] [blame] | 620 | #if defined(CONFIG_NOR) || defined(CONFIG_NAND) |
Ilya Yanok | 3d9725e | 2012-11-06 13:06:31 +0000 | [diff] [blame] | 621 | gpmc_init(); |
Steve Kipisz | be9b6f8 | 2013-07-18 15:13:03 -0400 | [diff] [blame] | 622 | #endif |
Lokesh Vutla | 0d144f5 | 2016-05-16 11:47:26 +0530 | [diff] [blame] | 623 | |
Alex Kiernan | 20bba2e | 2018-04-01 09:22:37 +0000 | [diff] [blame] | 624 | #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \ |
| 625 | (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))) |
Lokesh Vutla | 0d144f5 | 2016-05-16 11:47:26 +0530 | [diff] [blame] | 626 | if (board_is_icev2()) { |
Roger Quadros | bcb4ee8 | 2016-08-24 15:35:50 +0300 | [diff] [blame] | 627 | int rv; |
| 628 | u32 reg; |
| 629 | |
Lokesh Vutla | 0d144f5 | 2016-05-16 11:47:26 +0530 | [diff] [blame] | 630 | REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL); |
Roger Quadros | bcb4ee8 | 2016-08-24 15:35:50 +0300 | [diff] [blame] | 631 | /* Make J19 status available on GPIO1_26 */ |
| 632 | REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL); |
| 633 | |
Lokesh Vutla | 0d144f5 | 2016-05-16 11:47:26 +0530 | [diff] [blame] | 634 | REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL); |
Roger Quadros | bcb4ee8 | 2016-08-24 15:35:50 +0300 | [diff] [blame] | 635 | /* |
| 636 | * Both ports can be set as RMII-CPSW or MII-PRU-ETH using |
| 637 | * jumpers near the port. Read the jumper value and set |
| 638 | * the pinmux, external mux and PHY clock accordingly. |
| 639 | * As jumper line is overridden by PHY RX_DV pin immediately |
| 640 | * after bootstrap (power-up/reset), we need to sample |
| 641 | * it during PHY reset using GPIO rising edge detection. |
| 642 | */ |
Lokesh Vutla | 0d144f5 | 2016-05-16 11:47:26 +0530 | [diff] [blame] | 643 | REQUEST_AND_SET_GPIO(GPIO_PHY_RESET); |
Roger Quadros | bcb4ee8 | 2016-08-24 15:35:50 +0300 | [diff] [blame] | 644 | /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */ |
| 645 | reg = readl(GPIO0_RISINGDETECT) | BIT(11); |
| 646 | writel(reg, GPIO0_RISINGDETECT); |
| 647 | reg = readl(GPIO1_RISINGDETECT) | BIT(26); |
| 648 | writel(reg, GPIO1_RISINGDETECT); |
| 649 | /* Reset PHYs to capture the Jumper setting */ |
| 650 | gpio_set_value(GPIO_PHY_RESET, 0); |
| 651 | udelay(2); /* PHY datasheet states 1uS min. */ |
| 652 | gpio_set_value(GPIO_PHY_RESET, 1); |
| 653 | |
| 654 | reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11); |
| 655 | if (reg) { |
| 656 | writel(reg, GPIO0_IRQSTATUS1); /* clear irq */ |
| 657 | /* RMII mode */ |
| 658 | printf("ETH0, CPSW\n"); |
| 659 | } else { |
| 660 | /* MII mode */ |
| 661 | printf("ETH0, PRU\n"); |
| 662 | cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */ |
| 663 | } |
| 664 | |
| 665 | reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26); |
| 666 | if (reg) { |
| 667 | writel(reg, GPIO1_IRQSTATUS1); /* clear irq */ |
| 668 | /* RMII mode */ |
| 669 | printf("ETH1, CPSW\n"); |
| 670 | gpio_set_value(GPIO_MUX_MII_CTRL, 1); |
| 671 | } else { |
| 672 | /* MII mode */ |
| 673 | printf("ETH1, PRU\n"); |
| 674 | cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */ |
| 675 | } |
| 676 | |
| 677 | /* disable rising edge IRQs */ |
| 678 | reg = readl(GPIO0_RISINGDETECT) & ~BIT(11); |
| 679 | writel(reg, GPIO0_RISINGDETECT); |
| 680 | reg = readl(GPIO1_RISINGDETECT) & ~BIT(26); |
| 681 | writel(reg, GPIO1_RISINGDETECT); |
Lokesh Vutla | 0d144f5 | 2016-05-16 11:47:26 +0530 | [diff] [blame] | 682 | |
| 683 | rv = setup_clock_synthesizer(&cdce913_data); |
| 684 | if (rv) { |
| 685 | printf("Clock synthesizer setup failed %d\n", rv); |
| 686 | return rv; |
| 687 | } |
Roger Quadros | bcb4ee8 | 2016-08-24 15:35:50 +0300 | [diff] [blame] | 688 | |
| 689 | /* reset PHYs */ |
| 690 | gpio_set_value(GPIO_PHY_RESET, 0); |
| 691 | udelay(2); /* PHY datasheet states 1uS min. */ |
| 692 | gpio_set_value(GPIO_PHY_RESET, 1); |
Lokesh Vutla | 0d144f5 | 2016-05-16 11:47:26 +0530 | [diff] [blame] | 693 | } |
| 694 | #endif |
| 695 | |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 696 | return 0; |
| 697 | } |
| 698 | |
Tom Rini | 4027185 | 2012-10-24 07:28:17 +0000 | [diff] [blame] | 699 | #ifdef CONFIG_BOARD_LATE_INIT |
| 700 | int board_late_init(void) |
| 701 | { |
Roger Quadros | 7c9d378 | 2016-08-24 15:35:51 +0300 | [diff] [blame] | 702 | #if !defined(CONFIG_SPL_BUILD) |
| 703 | uint8_t mac_addr[6]; |
| 704 | uint32_t mac_hi, mac_lo; |
| 705 | #endif |
| 706 | |
Tom Rini | 4027185 | 2012-10-24 07:28:17 +0000 | [diff] [blame] | 707 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
Nishanth Menon | 2afa70d | 2016-02-24 12:30:55 -0600 | [diff] [blame] | 708 | char *name = NULL; |
Tom Rini | 4021fd9 | 2013-07-18 15:13:01 -0400 | [diff] [blame] | 709 | |
robertcnelson@gmail.com | c5d7d22 | 2017-03-30 14:29:52 -0500 | [diff] [blame] | 710 | if (board_is_bone_lt()) { |
| 711 | /* BeagleBoard.org BeagleBone Black Wireless: */ |
| 712 | if (!strncmp(board_ti_get_rev(), "BWA", 3)) { |
| 713 | name = "BBBW"; |
| 714 | } |
robertcnelson@gmail.com | b55cd7a | 2017-03-30 14:29:53 -0500 | [diff] [blame] | 715 | /* SeeedStudio BeagleBone Green Wireless */ |
| 716 | if (!strncmp(board_ti_get_rev(), "GW1", 3)) { |
| 717 | name = "BBGW"; |
| 718 | } |
robertcnelson@gmail.com | 89ef1d6 | 2017-03-30 14:29:54 -0500 | [diff] [blame] | 719 | /* BeagleBoard.org BeagleBone Blue */ |
| 720 | if (!strncmp(board_ti_get_rev(), "BLA", 3)) { |
| 721 | name = "BBBL"; |
| 722 | } |
robertcnelson@gmail.com | c5d7d22 | 2017-03-30 14:29:52 -0500 | [diff] [blame] | 723 | } |
| 724 | |
Nishanth Menon | 2afa70d | 2016-02-24 12:30:55 -0600 | [diff] [blame] | 725 | if (board_is_bbg1()) |
| 726 | name = "BBG1"; |
| 727 | set_board_info_env(name); |
Lokesh Vutla | 1eb0f54 | 2016-11-29 11:58:03 +0530 | [diff] [blame] | 728 | |
| 729 | /* |
| 730 | * Default FIT boot on HS devices. Non FIT images are not allowed |
| 731 | * on HS devices. |
| 732 | */ |
| 733 | if (get_device_type() == HS_DEVICE) |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 734 | env_set("boot_fit", "1"); |
Tom Rini | 4027185 | 2012-10-24 07:28:17 +0000 | [diff] [blame] | 735 | #endif |
| 736 | |
Roger Quadros | 7c9d378 | 2016-08-24 15:35:51 +0300 | [diff] [blame] | 737 | #if !defined(CONFIG_SPL_BUILD) |
| 738 | /* try reading mac address from efuse */ |
| 739 | mac_lo = readl(&cdev->macid0l); |
| 740 | mac_hi = readl(&cdev->macid0h); |
| 741 | mac_addr[0] = mac_hi & 0xFF; |
| 742 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
| 743 | mac_addr[2] = (mac_hi & 0xFF0000) >> 16; |
| 744 | mac_addr[3] = (mac_hi & 0xFF000000) >> 24; |
| 745 | mac_addr[4] = mac_lo & 0xFF; |
| 746 | mac_addr[5] = (mac_lo & 0xFF00) >> 8; |
| 747 | |
Simon Glass | 64b723f | 2017-08-03 12:22:12 -0600 | [diff] [blame] | 748 | if (!env_get("ethaddr")) { |
Roger Quadros | 7c9d378 | 2016-08-24 15:35:51 +0300 | [diff] [blame] | 749 | printf("<ethaddr> not set. Validating first E-fuse MAC\n"); |
| 750 | |
| 751 | if (is_valid_ethaddr(mac_addr)) |
Simon Glass | 8551d55 | 2017-08-03 12:22:11 -0600 | [diff] [blame] | 752 | eth_env_set_enetaddr("ethaddr", mac_addr); |
Roger Quadros | 7c9d378 | 2016-08-24 15:35:51 +0300 | [diff] [blame] | 753 | } |
| 754 | |
| 755 | mac_lo = readl(&cdev->macid1l); |
| 756 | mac_hi = readl(&cdev->macid1h); |
| 757 | mac_addr[0] = mac_hi & 0xFF; |
| 758 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
| 759 | mac_addr[2] = (mac_hi & 0xFF0000) >> 16; |
| 760 | mac_addr[3] = (mac_hi & 0xFF000000) >> 24; |
| 761 | mac_addr[4] = mac_lo & 0xFF; |
| 762 | mac_addr[5] = (mac_lo & 0xFF00) >> 8; |
| 763 | |
Simon Glass | 64b723f | 2017-08-03 12:22:12 -0600 | [diff] [blame] | 764 | if (!env_get("eth1addr")) { |
Roger Quadros | 7c9d378 | 2016-08-24 15:35:51 +0300 | [diff] [blame] | 765 | if (is_valid_ethaddr(mac_addr)) |
Simon Glass | 8551d55 | 2017-08-03 12:22:11 -0600 | [diff] [blame] | 766 | eth_env_set_enetaddr("eth1addr", mac_addr); |
Roger Quadros | 7c9d378 | 2016-08-24 15:35:51 +0300 | [diff] [blame] | 767 | } |
| 768 | #endif |
| 769 | |
Sam Protsenko | a31ca62 | 2018-02-28 00:26:15 +0200 | [diff] [blame] | 770 | if (!env_get("serial#")) { |
| 771 | char *board_serial = env_get("board_serial"); |
| 772 | char *ethaddr = env_get("ethaddr"); |
| 773 | |
| 774 | if (!board_serial || !strncmp(board_serial, "unknown", 7)) |
| 775 | env_set("serial#", ethaddr); |
| 776 | else |
| 777 | env_set("serial#", board_serial); |
| 778 | } |
| 779 | |
Tom Rini | 4027185 | 2012-10-24 07:28:17 +0000 | [diff] [blame] | 780 | return 0; |
| 781 | } |
| 782 | #endif |
| 783 | |
Mugunthan V N | df7a99f | 2015-09-07 14:22:18 +0530 | [diff] [blame] | 784 | #ifndef CONFIG_DM_ETH |
| 785 | |
Ilya Yanok | 0760a0d | 2013-02-05 11:36:26 +0000 | [diff] [blame] | 786 | #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ |
| 787 | (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 788 | static void cpsw_control(int enabled) |
| 789 | { |
| 790 | /* VTP can be added here */ |
| 791 | |
| 792 | return; |
| 793 | } |
| 794 | |
| 795 | static struct cpsw_slave_data cpsw_slaves[] = { |
| 796 | { |
| 797 | .slave_reg_ofs = 0x208, |
| 798 | .sliver_reg_ofs = 0xd80, |
Mugunthan V N | 4944f37 | 2014-02-18 07:31:52 -0500 | [diff] [blame] | 799 | .phy_addr = 0, |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 800 | }, |
| 801 | { |
| 802 | .slave_reg_ofs = 0x308, |
| 803 | .sliver_reg_ofs = 0xdc0, |
Mugunthan V N | 4944f37 | 2014-02-18 07:31:52 -0500 | [diff] [blame] | 804 | .phy_addr = 1, |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 805 | }, |
| 806 | }; |
| 807 | |
| 808 | static struct cpsw_platform_data cpsw_data = { |
Matt Porter | e24646f | 2013-03-15 10:07:02 +0000 | [diff] [blame] | 809 | .mdio_base = CPSW_MDIO_BASE, |
| 810 | .cpsw_base = CPSW_BASE, |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 811 | .mdio_div = 0xff, |
| 812 | .channels = 8, |
| 813 | .cpdma_reg_ofs = 0x800, |
| 814 | .slaves = 1, |
| 815 | .slave_data = cpsw_slaves, |
| 816 | .ale_reg_ofs = 0xd00, |
| 817 | .ale_entries = 1024, |
| 818 | .host_port_reg_ofs = 0x108, |
| 819 | .hw_stats_reg_ofs = 0x900, |
Mugunthan V N | ff55987 | 2013-07-08 16:04:37 +0530 | [diff] [blame] | 820 | .bd_ram_ofs = 0x2000, |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 821 | .mac_control = (1 << 5), |
| 822 | .control = cpsw_control, |
| 823 | .host_port_num = 0, |
| 824 | .version = CPSW_CTRL_VERSION_2, |
| 825 | }; |
Ilya Yanok | 44a2c07 | 2012-11-06 13:48:24 +0000 | [diff] [blame] | 826 | #endif |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 827 | |
Faiz Abbas | c01553b | 2018-02-16 21:17:44 +0530 | [diff] [blame] | 828 | #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) &&\ |
Lokesh Vutla | 0d144f5 | 2016-05-16 11:47:26 +0530 | [diff] [blame] | 829 | defined(CONFIG_SPL_BUILD)) || \ |
| 830 | ((defined(CONFIG_DRIVER_TI_CPSW) || \ |
| 831 | defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ |
| 832 | !defined(CONFIG_SPL_BUILD)) |
| 833 | |
Tom Rini | 60fcaaa | 2014-03-26 15:53:12 -0400 | [diff] [blame] | 834 | /* |
| 835 | * This function will: |
| 836 | * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr |
| 837 | * in the environment |
| 838 | * Perform fixups to the PHY present on certain boards. We only need this |
| 839 | * function in: |
| 840 | * - SPL with either CPSW or USB ethernet support |
| 841 | * - Full U-Boot, with either CPSW or USB ethernet |
| 842 | * Build in only these cases to avoid warnings about unused variables |
| 843 | * when we build an SPL that has neither option but full U-Boot will. |
| 844 | */ |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 845 | int board_eth_init(bd_t *bis) |
| 846 | { |
Ilya Yanok | 44a2c07 | 2012-11-06 13:48:24 +0000 | [diff] [blame] | 847 | int rv, n = 0; |
Roger Quadros | 7c9d378 | 2016-08-24 15:35:51 +0300 | [diff] [blame] | 848 | #if defined(CONFIG_USB_ETHER) && \ |
Faiz Abbas | c01553b | 2018-02-16 21:17:44 +0530 | [diff] [blame] | 849 | (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER)) |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 850 | uint8_t mac_addr[6]; |
| 851 | uint32_t mac_hi, mac_lo; |
| 852 | |
Roger Quadros | 7c9d378 | 2016-08-24 15:35:51 +0300 | [diff] [blame] | 853 | /* |
| 854 | * use efuse mac address for USB ethernet as we know that |
| 855 | * both CPSW and USB ethernet will never be active at the same time |
| 856 | */ |
Ilya Yanok | 0760a0d | 2013-02-05 11:36:26 +0000 | [diff] [blame] | 857 | mac_lo = readl(&cdev->macid0l); |
| 858 | mac_hi = readl(&cdev->macid0h); |
| 859 | mac_addr[0] = mac_hi & 0xFF; |
| 860 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
| 861 | mac_addr[2] = (mac_hi & 0xFF0000) >> 16; |
| 862 | mac_addr[3] = (mac_hi & 0xFF000000) >> 24; |
| 863 | mac_addr[4] = mac_lo & 0xFF; |
| 864 | mac_addr[5] = (mac_lo & 0xFF00) >> 8; |
Roger Quadros | 7c9d378 | 2016-08-24 15:35:51 +0300 | [diff] [blame] | 865 | #endif |
| 866 | |
Ilya Yanok | 0760a0d | 2013-02-05 11:36:26 +0000 | [diff] [blame] | 867 | |
| 868 | #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ |
| 869 | (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 870 | |
Joel A Fernandes | f748854 | 2013-05-07 05:52:55 +0000 | [diff] [blame] | 871 | #ifdef CONFIG_DRIVER_TI_CPSW |
Nishanth Menon | 2afa70d | 2016-02-24 12:30:55 -0600 | [diff] [blame] | 872 | if (board_is_bone() || board_is_bone_lt() || |
| 873 | board_is_idk()) { |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 874 | writel(MII_MODE_ENABLE, &cdev->miisel); |
| 875 | cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = |
| 876 | PHY_INTERFACE_MODE_MII; |
Lokesh Vutla | 0d144f5 | 2016-05-16 11:47:26 +0530 | [diff] [blame] | 877 | } else if (board_is_icev2()) { |
| 878 | writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); |
| 879 | cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; |
| 880 | cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII; |
| 881 | cpsw_slaves[0].phy_addr = 1; |
| 882 | cpsw_slaves[1].phy_addr = 3; |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 883 | } else { |
Heiko Schocher | c4fea29 | 2013-08-19 16:38:56 +0200 | [diff] [blame] | 884 | writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 885 | cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = |
| 886 | PHY_INTERFACE_MODE_RGMII; |
| 887 | } |
| 888 | |
Ilya Yanok | 44a2c07 | 2012-11-06 13:48:24 +0000 | [diff] [blame] | 889 | rv = cpsw_register(&cpsw_data); |
| 890 | if (rv < 0) |
| 891 | printf("Error %d registering CPSW switch\n", rv); |
| 892 | else |
| 893 | n += rv; |
Joel A Fernandes | f748854 | 2013-05-07 05:52:55 +0000 | [diff] [blame] | 894 | #endif |
Tom Rini | 183943d | 2013-02-12 14:59:23 -0500 | [diff] [blame] | 895 | |
| 896 | /* |
| 897 | * |
| 898 | * CPSW RGMII Internal Delay Mode is not supported in all PVT |
| 899 | * operating points. So we must set the TX clock delay feature |
| 900 | * in the AR8051 PHY. Since we only support a single ethernet |
| 901 | * device in U-Boot, we only do this for the first instance. |
| 902 | */ |
| 903 | #define AR8051_PHY_DEBUG_ADDR_REG 0x1d |
| 904 | #define AR8051_PHY_DEBUG_DATA_REG 0x1e |
| 905 | #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 |
| 906 | #define AR8051_RGMII_TX_CLK_DLY 0x100 |
| 907 | |
Nishanth Menon | 2afa70d | 2016-02-24 12:30:55 -0600 | [diff] [blame] | 908 | if (board_is_evm_sk() || board_is_gp_evm()) { |
Tom Rini | 183943d | 2013-02-12 14:59:23 -0500 | [diff] [blame] | 909 | const char *devname; |
| 910 | devname = miiphy_get_current_dev(); |
| 911 | |
| 912 | miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, |
| 913 | AR8051_DEBUG_RGMII_CLK_DLY_REG); |
| 914 | miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, |
| 915 | AR8051_RGMII_TX_CLK_DLY); |
| 916 | } |
Ilya Yanok | 44a2c07 | 2012-11-06 13:48:24 +0000 | [diff] [blame] | 917 | #endif |
Ilya Yanok | 0760a0d | 2013-02-05 11:36:26 +0000 | [diff] [blame] | 918 | #if defined(CONFIG_USB_ETHER) && \ |
Faiz Abbas | c01553b | 2018-02-16 21:17:44 +0530 | [diff] [blame] | 919 | (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER)) |
Joe Hershberger | 8ecdbed | 2015-04-08 01:41:04 -0500 | [diff] [blame] | 920 | if (is_valid_ethaddr(mac_addr)) |
Simon Glass | 8551d55 | 2017-08-03 12:22:11 -0600 | [diff] [blame] | 921 | eth_env_set_enetaddr("usbnet_devaddr", mac_addr); |
Ilya Yanok | 0760a0d | 2013-02-05 11:36:26 +0000 | [diff] [blame] | 922 | |
Ilya Yanok | 44a2c07 | 2012-11-06 13:48:24 +0000 | [diff] [blame] | 923 | rv = usb_eth_initialize(bis); |
| 924 | if (rv < 0) |
| 925 | printf("Error %d registering USB_ETHER\n", rv); |
| 926 | else |
| 927 | n += rv; |
| 928 | #endif |
| 929 | return n; |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 930 | } |
| 931 | #endif |
Mugunthan V N | df7a99f | 2015-09-07 14:22:18 +0530 | [diff] [blame] | 932 | |
| 933 | #endif /* CONFIG_DM_ETH */ |
Lokesh Vutla | 89b9f30 | 2016-05-16 11:24:24 +0530 | [diff] [blame] | 934 | |
| 935 | #ifdef CONFIG_SPL_LOAD_FIT |
| 936 | int board_fit_config_name_match(const char *name) |
| 937 | { |
| 938 | if (board_is_gp_evm() && !strcmp(name, "am335x-evm")) |
| 939 | return 0; |
| 940 | else if (board_is_bone() && !strcmp(name, "am335x-bone")) |
| 941 | return 0; |
| 942 | else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack")) |
| 943 | return 0; |
Jason Kridner | b56b5b3 | 2018-03-07 05:40:41 -0500 | [diff] [blame] | 944 | else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle")) |
| 945 | return 0; |
Lokesh Vutla | 5a954ba | 2016-05-16 11:24:28 +0530 | [diff] [blame] | 946 | else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk")) |
| 947 | return 0; |
Lokesh Vutla | 1edfcaf | 2016-05-16 11:24:29 +0530 | [diff] [blame] | 948 | else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen")) |
| 949 | return 0; |
Lokesh Vutla | 7ecf196 | 2016-05-16 11:47:28 +0530 | [diff] [blame] | 950 | else if (board_is_icev2() && !strcmp(name, "am335x-icev2")) |
| 951 | return 0; |
Lokesh Vutla | 89b9f30 | 2016-05-16 11:24:24 +0530 | [diff] [blame] | 952 | else |
| 953 | return -1; |
| 954 | } |
| 955 | #endif |
Andrew F. Davis | bd24915 | 2016-08-30 14:06:24 -0500 | [diff] [blame] | 956 | |
| 957 | #ifdef CONFIG_TI_SECURE_DEVICE |
| 958 | void board_fit_image_post_process(void **p_image, size_t *p_size) |
| 959 | { |
| 960 | secure_boot_verify_image(p_image, p_size); |
| 961 | } |
| 962 | #endif |
Lokesh Vutla | 2fe7c79 | 2017-04-26 13:37:08 +0530 | [diff] [blame] | 963 | |
| 964 | #if !CONFIG_IS_ENABLED(OF_CONTROL) |
| 965 | static const struct omap_hsmmc_plat am335x_mmc0_platdata = { |
| 966 | .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE, |
| 967 | .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT, |
| 968 | .cfg.f_min = 400000, |
| 969 | .cfg.f_max = 52000000, |
| 970 | .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195, |
| 971 | .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, |
| 972 | }; |
| 973 | |
| 974 | U_BOOT_DEVICE(am335x_mmc0) = { |
| 975 | .name = "omap_hsmmc", |
| 976 | .platdata = &am335x_mmc0_platdata, |
| 977 | }; |
| 978 | |
| 979 | static const struct omap_hsmmc_plat am335x_mmc1_platdata = { |
| 980 | .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE, |
| 981 | .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT, |
| 982 | .cfg.f_min = 400000, |
| 983 | .cfg.f_max = 52000000, |
| 984 | .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195, |
| 985 | .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, |
| 986 | }; |
| 987 | |
| 988 | U_BOOT_DEVICE(am335x_mmc1) = { |
| 989 | .name = "omap_hsmmc", |
| 990 | .platdata = &am335x_mmc1_platdata, |
| 991 | }; |
| 992 | #endif |