blob: fe4b6a91d20797bc48a7ef5e5da07a5153e43024 [file] [log] [blame]
wdenkb02744a2003-04-05 00:53:31 +00001/*
2 * Copyright (C) 2003 ETC s.r.o.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *
19 * Written by Peter Figuli <peposh@etc.sk>, 2003.
20 *
21 */
22
23#include <common.h>
24#include <asm/arch/pxa-regs.h>
25
Wolfgang Denk6405a152006-03-31 18:32:53 +020026DECLARE_GLOBAL_DATA_PTR;
wdenkb02744a2003-04-05 00:53:31 +000027
Wolfgang Denk6405a152006-03-31 18:32:53 +020028int board_init (void)
29{
30 gd->bd->bi_arch_number = MACH_TYPE_WEP_EP250;
31 gd->bd->bi_boot_params = 0xa0000000;
wdenkb02744a2003-04-05 00:53:31 +000032/*
33 * Setup GPIO stuff to get serial working
34 */
35#if defined( CONFIG_FFUART )
Wolfgang Denk6405a152006-03-31 18:32:53 +020036 GPDR1 = 0x80;
37 GAFR1_L = 0x8010;
wdenkb02744a2003-04-05 00:53:31 +000038#elif defined( CONFIG_BTUART )
Wolfgang Denk6405a152006-03-31 18:32:53 +020039 GPDR1 = 0x800;
40 GAFR1_L = 0x900000;
wdenkb02744a2003-04-05 00:53:31 +000041#endif
Wolfgang Denk6405a152006-03-31 18:32:53 +020042 PSSR = 0x20;
wdenkb02744a2003-04-05 00:53:31 +000043
Wolfgang Denk6405a152006-03-31 18:32:53 +020044 return 0;
wdenkb02744a2003-04-05 00:53:31 +000045}
46
Wolfgang Denk6405a152006-03-31 18:32:53 +020047int dram_init (void)
48{
wdenkb02744a2003-04-05 00:53:31 +000049#if ( CONFIG_NR_DRAM_BANKS > 0 )
Wolfgang Denk6405a152006-03-31 18:32:53 +020050 gd->bd->bi_dram[0].start = WEP_SDRAM_1;
51 gd->bd->bi_dram[0].size = WEP_SDRAM_1_SIZE;
wdenkb02744a2003-04-05 00:53:31 +000052#endif
wdenk57b2d802003-06-27 21:31:46 +000053#if ( CONFIG_NR_DRAM_BANKS > 1 )
Wolfgang Denk6405a152006-03-31 18:32:53 +020054 gd->bd->bi_dram[1].start = WEP_SDRAM_2;
55 gd->bd->bi_dram[1].size = WEP_SDRAM_2_SIZE;
wdenkb02744a2003-04-05 00:53:31 +000056#endif
wdenk57b2d802003-06-27 21:31:46 +000057#if ( CONFIG_NR_DRAM_BANKS > 2 )
Wolfgang Denk6405a152006-03-31 18:32:53 +020058 gd->bd->bi_dram[2].start = WEP_SDRAM_3;
59 gd->bd->bi_dram[2].size = WEP_SDRAM_3_SIZE;
wdenkb02744a2003-04-05 00:53:31 +000060#endif
61#if ( CONFIG_NR_DRAM_BANKS > 3 )
Wolfgang Denk6405a152006-03-31 18:32:53 +020062 gd->bd->bi_dram[3].start = WEP_SDRAM_4;
63 gd->bd->bi_dram[3].size = WEP_SDRAM_4_SIZE;
wdenkb02744a2003-04-05 00:53:31 +000064#endif
wdenk57b2d802003-06-27 21:31:46 +000065
Wolfgang Denk6405a152006-03-31 18:32:53 +020066 return 0;
wdenkb02744a2003-04-05 00:53:31 +000067}