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git01.mediatek.com / filogic / uboot / f87959b153b6f2ee7dc38aaf0f799283a33193b6 / . / arch / mips / mach-jz47xx / jz4780 / timer.c
blob: 988ebd26715ca89064e45f0e393dabdf8ef05c64 [file] [log] [blame]
Paul Burton96c68472018-12-16 19:25:22 -0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * JZ4780 timer
4 *
5 * Copyright (c) 2013 Imagination Technologies
6 * Author: Paul Burton <paul.burton@imgtec.com>
7 */
8
9#include <config.h>
10#include <common.h>
11#include <div64.h>
Simon Glass495a5dc2019-11-14 12:57:30 -0700[diff] [blame]12#include <time.h>
Paul Burton96c68472018-12-16 19:25:22 -0300[diff] [blame]13#include <asm/io.h>
14#include <asm/mipsregs.h>
15#include <mach/jz4780.h>
16
17#define TCU_TSR 0x1C /* Timer Stop Register */
18#define TCU_TSSR 0x2C /* Timer Stop Set Register */
19#define TCU_TSCR 0x3C /* Timer Stop Clear Register */
20#define TCU_TER 0x10 /* Timer Counter Enable Register */
21#define TCU_TESR 0x14 /* Timer Counter Enable Set Register */
22#define TCU_TECR 0x18 /* Timer Counter Enable Clear Register */
23#define TCU_TFR 0x20 /* Timer Flag Register */
24#define TCU_TFSR 0x24 /* Timer Flag Set Register */
25#define TCU_TFCR 0x28 /* Timer Flag Clear Register */
26#define TCU_TMR 0x30 /* Timer Mask Register */
27#define TCU_TMSR 0x34 /* Timer Mask Set Register */
28#define TCU_TMCR 0x38 /* Timer Mask Clear Register */
29/* n = 0,1,2,3,4,5 */
30#define TCU_TDFR(n) (0x40 + (n) * 0x10) /* Timer Data Full Reg */
31#define TCU_TDHR(n) (0x44 + (n) * 0x10) /* Timer Data Half Reg */
32#define TCU_TCNT(n) (0x48 + (n) * 0x10) /* Timer Counter Reg */
33#define TCU_TCSR(n) (0x4C + (n) * 0x10) /* Timer Control Reg */
34
35#define TCU_OSTCNTL 0xe4
36#define TCU_OSTCNTH 0xe8
37#define TCU_OSTCSR 0xec
38#define TCU_OSTCNTHBUF 0xfc
39
40/* Register definitions */
41#define TCU_TCSR_PWM_SD BIT(9)
42#define TCU_TCSR_PWM_INITL_HIGH BIT(8)
43#define TCU_TCSR_PWM_EN BIT(7)
44#define TCU_TCSR_PRESCALE_BIT 3
45#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
46#define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
47#define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
48#define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
49#define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
50#define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
51#define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
52#define TCU_TCSR_EXT_EN BIT(2)
53#define TCU_TCSR_RTC_EN BIT(1)
54#define TCU_TCSR_PCK_EN BIT(0)
55
56#define TCU_TER_TCEN5 BIT(5)
57#define TCU_TER_TCEN4 BIT(4)
58#define TCU_TER_TCEN3 BIT(3)
59#define TCU_TER_TCEN2 BIT(2)
60#define TCU_TER_TCEN1 BIT(1)
61#define TCU_TER_TCEN0 BIT(0)
62
63#define TCU_TESR_TCST5 BIT(5)
64#define TCU_TESR_TCST4 BIT(4)
65#define TCU_TESR_TCST3 BIT(3)
66#define TCU_TESR_TCST2 BIT(2)
67#define TCU_TESR_TCST1 BIT(1)
68#define TCU_TESR_TCST0 BIT(0)
69
70#define TCU_TECR_TCCL5 BIT(5)
71#define TCU_TECR_TCCL4 BIT(4)
72#define TCU_TECR_TCCL3 BIT(3)
73#define TCU_TECR_TCCL2 BIT(2)
74#define TCU_TECR_TCCL1 BIT(1)
75#define TCU_TECR_TCCL0 BIT(0)
76
77#define TCU_TFR_HFLAG5 BIT(21)
78#define TCU_TFR_HFLAG4 BIT(20)
79#define TCU_TFR_HFLAG3 BIT(19)
80#define TCU_TFR_HFLAG2 BIT(18)
81#define TCU_TFR_HFLAG1 BIT(17)
82#define TCU_TFR_HFLAG0 BIT(16)
83#define TCU_TFR_FFLAG5 BIT(5)
84#define TCU_TFR_FFLAG4 BIT(4)
85#define TCU_TFR_FFLAG3 BIT(3)
86#define TCU_TFR_FFLAG2 BIT(2)
87#define TCU_TFR_FFLAG1 BIT(1)
88#define TCU_TFR_FFLAG0 BIT(0)
89
90#define TCU_TFSR_HFLAG5 BIT(21)
91#define TCU_TFSR_HFLAG4 BIT(20)
92#define TCU_TFSR_HFLAG3 BIT(19)
93#define TCU_TFSR_HFLAG2 BIT(18)
94#define TCU_TFSR_HFLAG1 BIT(17)
95#define TCU_TFSR_HFLAG0 BIT(16)
96#define TCU_TFSR_FFLAG5 BIT(5)
97#define TCU_TFSR_FFLAG4 BIT(4)
98#define TCU_TFSR_FFLAG3 BIT(3)
99#define TCU_TFSR_FFLAG2 BIT(2)
100#define TCU_TFSR_FFLAG1 BIT(1)
101#define TCU_TFSR_FFLAG0 BIT(0)
102
103#define TCU_TFCR_HFLAG5 BIT(21)
104#define TCU_TFCR_HFLAG4 BIT(20)
105#define TCU_TFCR_HFLAG3 BIT(19)
106#define TCU_TFCR_HFLAG2 BIT(18)
107#define TCU_TFCR_HFLAG1 BIT(17)
108#define TCU_TFCR_HFLAG0 BIT(16)
109#define TCU_TFCR_FFLAG5 BIT(5)
110#define TCU_TFCR_FFLAG4 BIT(4)
111#define TCU_TFCR_FFLAG3 BIT(3)
112#define TCU_TFCR_FFLAG2 BIT(2)
113#define TCU_TFCR_FFLAG1 BIT(1)
114#define TCU_TFCR_FFLAG0 BIT(0)
115
116#define TCU_TMR_HMASK5 BIT(21)
117#define TCU_TMR_HMASK4 BIT(20)
118#define TCU_TMR_HMASK3 BIT(19)
119#define TCU_TMR_HMASK2 BIT(18)
120#define TCU_TMR_HMASK1 BIT(17)
121#define TCU_TMR_HMASK0 BIT(16)
122#define TCU_TMR_FMASK5 BIT(5)
123#define TCU_TMR_FMASK4 BIT(4)
124#define TCU_TMR_FMASK3 BIT(3)
125#define TCU_TMR_FMASK2 BIT(2)
126#define TCU_TMR_FMASK1 BIT(1)
127#define TCU_TMR_FMASK0 BIT(0)
128
129#define TCU_TMSR_HMST5 BIT(21)
130#define TCU_TMSR_HMST4 BIT(20)
131#define TCU_TMSR_HMST3 BIT(19)
132#define TCU_TMSR_HMST2 BIT(18)
133#define TCU_TMSR_HMST1 BIT(17)
134#define TCU_TMSR_HMST0 BIT(16)
135#define TCU_TMSR_FMST5 BIT(5)
136#define TCU_TMSR_FMST4 BIT(4)
137#define TCU_TMSR_FMST3 BIT(3)
138#define TCU_TMSR_FMST2 BIT(2)
139#define TCU_TMSR_FMST1 BIT(1)
140#define TCU_TMSR_FMST0 BIT(0)
141
142#define TCU_TMCR_HMCL5 BIT(21)
143#define TCU_TMCR_HMCL4 BIT(20)
144#define TCU_TMCR_HMCL3 BIT(19)
145#define TCU_TMCR_HMCL2 BIT(18)
146#define TCU_TMCR_HMCL1 BIT(17)
147#define TCU_TMCR_HMCL0 BIT(16)
148#define TCU_TMCR_FMCL5 BIT(5)
149#define TCU_TMCR_FMCL4 BIT(4)
150#define TCU_TMCR_FMCL3 BIT(3)
151#define TCU_TMCR_FMCL2 BIT(2)
152#define TCU_TMCR_FMCL1 BIT(1)
153#define TCU_TMCR_FMCL0 BIT(0)
154
155#define TCU_TSR_WDTS BIT(16)
156#define TCU_TSR_STOP5 BIT(5)
157#define TCU_TSR_STOP4 BIT(4)
158#define TCU_TSR_STOP3 BIT(3)
159#define TCU_TSR_STOP2 BIT(2)
160#define TCU_TSR_STOP1 BIT(1)
161#define TCU_TSR_STOP0 BIT(0)
162
163#define TCU_TSSR_WDTSS BIT(16)
164#define TCU_TSSR_STPS5 BIT(5)
165#define TCU_TSSR_STPS4 BIT(4)
166#define TCU_TSSR_STPS3 BIT(3)
167#define TCU_TSSR_STPS2 BIT(2)
168#define TCU_TSSR_STPS1 BIT(1)
169#define TCU_TSSR_STPS0 BIT(0)
170
171#define TCU_TSSR_WDTSC BIT(16)
172#define TCU_TSSR_STPC5 BIT(5)
173#define TCU_TSSR_STPC4 BIT(4)
174#define TCU_TSSR_STPC3 BIT(3)
175#define TCU_TSSR_STPC2 BIT(2)
176#define TCU_TSSR_STPC1 BIT(1)
177#define TCU_TSSR_STPC0 BIT(0)
178
179#define TER_OSTEN BIT(15)
180
181#define OSTCSR_CNT_MD BIT(15)
182#define OSTCSR_SD BIT(9)
183#define OSTCSR_PRESCALE_16 (0x2 << 3)
184#define OSTCSR_EXT_EN BIT(2)
185
186int timer_init(void)
187{
188 void __iomem *regs = (void __iomem *)TCU_BASE;
189
190 writel(OSTCSR_SD, regs + TCU_OSTCSR);
191 reset_timer();
192 writel(OSTCSR_CNT_MD | OSTCSR_EXT_EN | OSTCSR_PRESCALE_16,
193 regs + TCU_OSTCSR);
194 writew(TER_OSTEN, regs + TCU_TESR);
195 return 0;
196}
197
198void reset_timer(void)
199{
200 void __iomem *regs = (void __iomem *)TCU_BASE;
201
202 writel(0, regs + TCU_OSTCNTH);
203 writel(0, regs + TCU_OSTCNTL);
204}
205
206static u64 get_timer64(void)
207{
208 void __iomem *regs = (void __iomem *)TCU_BASE;
209 u32 low = readl(regs + TCU_OSTCNTL);
210 u32 high = readl(regs + TCU_OSTCNTHBUF);
211
212 return ((u64)high << 32) | low;
213}
214
215ulong get_timer(ulong base)
216{
217 return lldiv(get_timer64(), 3000) - base;
218}
219
220void __udelay(unsigned long usec)
221{
222 /* OST count increments at 3MHz */
223 u64 end = get_timer64() + ((u64)usec * 3);
224
225 while (get_timer64() < end)
226 ;
227}
228
229unsigned long long get_ticks(void)
230{
231 return get_timer64();
232}
233
234void jz4780_tcu_wdt_start(void)
235{
236 void __iomem *tcu_regs = (void __iomem *)TCU_BASE;
237
238 /* Enable WDT clock */
239 writel(TCU_TSSR_WDTSC, tcu_regs + TCU_TSCR);
240}