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git01.mediatek.com / filogic / uboot / 9ac338549c3b904e2f02e03ec96dc2a27a0b71ca / . / configs / coreboot-x86_defconfig
blob: 438e43b4665f83978caa2f4b4d8c0b9d35be8143 [file] [log] [blame]
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]1CONFIG_X86=y
Bin Mengf9bfac12015-05-07 21:34:09 +0800[diff] [blame]2CONFIG_VENDOR_COREBOOT=y
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]3CONFIG_TARGET_COREBOOT=y
Joe Hershberger17491a82015-06-22 16:15:29 -0500[diff] [blame]4CONFIG_TSC_CALIBRATION_BYPASS=y
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]5# CONFIG_CMD_IMLS is not set
6# CONFIG_CMD_FLASH is not set
7# CONFIG_CMD_SETEXPR is not set
8# CONFIG_CMD_NFS is not set
Joe Hershberger17491a82015-06-22 16:15:29 -0500[diff] [blame]9CONFIG_BOOTSTAGE=y
10CONFIG_BOOTSTAGE_REPORT=y
11CONFIG_CMD_BOOTSTAGE=y
Simon Glass347a6222015-08-22 18:31:39 -0600[diff] [blame]12CONFIG_CMD_TPM=y
Simon Glass81ab5472015-08-22 18:31:43 -0600[diff] [blame]13CONFIG_CMD_TPM_TEST=y
Masahiro Yamada9fadbc82014-09-22 19:59:05 +0900[diff] [blame]14CONFIG_OF_CONTROL=y
Joe Hershberger17491a82015-06-22 16:15:29 -0500[diff] [blame]15CONFIG_SPI_FLASH=y
Bin Mengc35328a2015-08-28 02:22:38 -0700[diff] [blame]16CONFIG_DM_ETH=y
Simon Glass9008a5b2015-08-19 09:33:43 -0600[diff] [blame]17CONFIG_E1000=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]18CONFIG_DM_PCI=y
19CONFIG_DM_RTC=y
Simon Glass347a6222015-08-22 18:31:39 -0600[diff] [blame]20CONFIG_DM_TPM=y
Simon Glass8b6216a2015-08-22 18:31:20 -0600[diff] [blame]21CONFIG_TPM_TIS_LPC=y
Bin Mengc35328a2015-08-28 02:22:38 -0700[diff] [blame]22CONFIG_USB=y
23CONFIG_DM_USB=y
Joe Hershberger17491a82015-06-22 16:15:29 -0500[diff] [blame]24CONFIG_USE_PRIVATE_LIBGCC=y
25CONFIG_SYS_VSNPRINTF=y
Simon Glass8b6216a2015-08-22 18:31:20 -0600[diff] [blame]26CONFIG_TPM=y