Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 1 | CONFIG_PPC=y |
Tom Rini | 07edfae | 2018-02-03 12:10:38 -0500 | [diff] [blame] | 2 | CONFIG_SYS_TEXT_BASE=0xFE000000 |
Mario Six | d10f318 | 2019-01-21 09:17:53 +0100 | [diff] [blame] | 3 | CONFIG_SYS_CLK_FREQ=32000000 |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 4 | CONFIG_MPC83xx=y |
Mario Six | 4a50e56 | 2019-01-21 09:17:56 +0100 | [diff] [blame] | 5 | CONFIG_HIGH_BATS=y |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 6 | CONFIG_TARGET_VE8313=y |
Mario Six | 9486710 | 2019-01-21 09:17:54 +0100 | [diff] [blame] | 7 | CONFIG_SYSTEM_PLL_FACTOR_4_1=y |
| 8 | CONFIG_CORE_PLL_RATIO_25_1=y |
| 9 | CONFIG_PCI_HOST_MODE_ENABLE=y |
| 10 | CONFIG_PCI_INT_ARBITER1_ENABLE=y |
| 11 | CONFIG_BOOT_MEMORY_SPACE_LOW=y |
| 12 | CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y |
| 13 | CONFIG_LALE_TIMING_EARLIER=y |
Mario Six | a861ea6 | 2019-01-21 09:17:57 +0100 | [diff] [blame] | 14 | CONFIG_BAT0=y |
| 15 | CONFIG_BAT0_NAME="SDRAM" |
| 16 | CONFIG_BAT0_BASE=0x00000000 |
| 17 | CONFIG_BAT0_LENGTH_256_MBYTES=y |
| 18 | CONFIG_BAT0_ACCESS_RW=y |
| 19 | CONFIG_BAT0_USER_MODE_VALID=y |
| 20 | CONFIG_BAT0_SUPERVISOR_MODE_VALID=y |
| 21 | CONFIG_BAT1=y |
| 22 | CONFIG_BAT1_NAME="PCI_MEM" |
| 23 | CONFIG_BAT1_BASE=0x80000000 |
| 24 | CONFIG_BAT1_LENGTH_256_MBYTES=y |
| 25 | CONFIG_BAT1_ACCESS_RW=y |
| 26 | CONFIG_BAT1_USER_MODE_VALID=y |
| 27 | CONFIG_BAT1_SUPERVISOR_MODE_VALID=y |
| 28 | CONFIG_BAT2=y |
| 29 | CONFIG_BAT2_NAME="PCI_MMIO" |
| 30 | CONFIG_BAT2_BASE=0x90000000 |
| 31 | CONFIG_BAT2_LENGTH_256_MBYTES=y |
| 32 | CONFIG_BAT2_ACCESS_RW=y |
| 33 | CONFIG_BAT2_ICACHE_INHIBITED=y |
| 34 | CONFIG_BAT2_ICACHE_GUARDED=y |
| 35 | CONFIG_BAT2_DCACHE_INHIBITED=y |
| 36 | CONFIG_BAT2_DCACHE_GUARDED=y |
| 37 | CONFIG_BAT2_USER_MODE_VALID=y |
| 38 | CONFIG_BAT2_SUPERVISOR_MODE_VALID=y |
| 39 | CONFIG_BAT5=y |
| 40 | CONFIG_BAT5_NAME="IMMR_PCIIO_BCSR" |
| 41 | CONFIG_BAT5_BASE=0xE0000000 |
| 42 | CONFIG_BAT5_LENGTH_256_MBYTES=y |
| 43 | CONFIG_BAT5_ACCESS_RW=y |
| 44 | CONFIG_BAT5_ICACHE_INHIBITED=y |
| 45 | CONFIG_BAT5_ICACHE_GUARDED=y |
| 46 | CONFIG_BAT5_DCACHE_INHIBITED=y |
| 47 | CONFIG_BAT5_DCACHE_GUARDED=y |
| 48 | CONFIG_BAT5_USER_MODE_VALID=y |
| 49 | CONFIG_BAT5_SUPERVISOR_MODE_VALID=y |
| 50 | CONFIG_BAT6=y |
| 51 | CONFIG_BAT6_NAME="INITRAM_FLASH" |
| 52 | CONFIG_BAT6_BASE=0xF0000000 |
| 53 | CONFIG_BAT6_LENGTH_256_MBYTES=y |
| 54 | CONFIG_BAT6_ACCESS_RW=y |
| 55 | CONFIG_BAT6_ICACHE_GUARDED=y |
| 56 | CONFIG_BAT6_DCACHE_GUARDED=y |
| 57 | CONFIG_BAT6_USER_MODE_VALID=y |
| 58 | CONFIG_BAT6_SUPERVISOR_MODE_VALID=y |
| 59 | CONFIG_BAT7=y |
| 60 | CONFIG_BAT7_NAME="FPGA_SRAM_NAND" |
| 61 | CONFIG_BAT7_BASE=0x60000000 |
| 62 | CONFIG_BAT7_LENGTH_256_MBYTES=y |
| 63 | CONFIG_BAT7_ACCESS_RW=y |
| 64 | CONFIG_BAT7_ICACHE_GUARDED=y |
| 65 | CONFIG_BAT7_DCACHE_GUARDED=y |
| 66 | CONFIG_BAT7_USER_MODE_VALID=y |
| 67 | CONFIG_BAT7_SUPERVISOR_MODE_VALID=y |
Mario Six | b47839c | 2019-01-21 09:17:58 +0100 | [diff] [blame] | 68 | CONFIG_NAND_LBLAWBAR_PRELIM_1=y |
| 69 | CONFIG_LBLAW0=y |
| 70 | CONFIG_LBLAW0_BASE=0xFE000000 |
| 71 | CONFIG_LBLAW0_NAME="FLASH" |
| 72 | CONFIG_LBLAW0_LENGTH_32_MBYTES=y |
| 73 | CONFIG_LBLAW1=y |
| 74 | CONFIG_LBLAW1_BASE=0x61000000 |
| 75 | CONFIG_LBLAW1_NAME="NAND" |
| 76 | CONFIG_LBLAW1_LENGTH_32_KBYTES=y |
Mario Six | 8b2141c | 2019-01-21 09:18:09 +0100 | [diff] [blame] | 77 | CONFIG_HID0_FINAL_EMCP=y |
| 78 | CONFIG_HID0_FINAL_ICE=y |
| 79 | CONFIG_HID2_HBE=y |
Mario Six | aa50254 | 2019-01-21 09:18:12 +0100 | [diff] [blame] | 80 | CONFIG_ACR_PIPE_DEP_4=y |
| 81 | CONFIG_ACR_RPTCNT_4=y |
Simon Glass | e3ee2fb | 2016-02-22 22:55:43 -0700 | [diff] [blame] | 82 | CONFIG_OF_BOARD_SETUP=y |
| 83 | CONFIG_OF_STDOUT_VIA_ALIAS=y |
Heiko Schocher | 0b368b1 | 2016-06-07 08:31:14 +0200 | [diff] [blame] | 84 | CONFIG_BOOTDELAY=6 |
Simon Glass | 7a99a87 | 2017-01-23 13:31:20 -0700 | [diff] [blame] | 85 | CONFIG_BOARD_EARLY_INIT_F=y |
Tom Rini | f852e73 | 2016-04-21 21:37:19 -0400 | [diff] [blame] | 86 | CONFIG_HUSH_PARSER=y |
Tuomas Tynkkynen | 28d56bd | 2017-10-08 21:48:01 +0300 | [diff] [blame] | 87 | CONFIG_CMD_IMLS=y |
Tom Rini | 00448d2 | 2017-07-28 21:31:42 -0400 | [diff] [blame] | 88 | CONFIG_CMD_NAND=y |
Simon Glass | c88a09a | 2017-08-04 16:34:34 -0600 | [diff] [blame] | 89 | CONFIG_CMD_PCI=y |
Joe Hershberger | 5a9d7f1 | 2015-06-22 16:15:30 -0500 | [diff] [blame] | 90 | # CONFIG_CMD_SETEXPR is not set |
Tom Rini | 0f2dcb9 | 2016-04-22 16:41:25 -0400 | [diff] [blame] | 91 | CONFIG_CMD_DHCP=y |
Tom Rini | 1d9ac83 | 2016-04-24 17:29:26 -0400 | [diff] [blame] | 92 | CONFIG_CMD_MII=y |
Tom Rini | 0f2dcb9 | 2016-04-22 16:41:25 -0400 | [diff] [blame] | 93 | CONFIG_CMD_PING=y |
Tom Rini | 9834b90 | 2017-03-13 13:48:42 -0400 | [diff] [blame] | 94 | # CONFIG_MMC is not set |
Masahiro Yamada | 8cea9b5 | 2017-02-11 22:43:54 +0900 | [diff] [blame] | 95 | CONFIG_MTD_NOR_FLASH=y |
Adam Ford | 76da1b2 | 2018-10-14 15:10:50 -0500 | [diff] [blame] | 96 | CONFIG_FLASH_CFI_DRIVER=y |
| 97 | CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y |
| 98 | CONFIG_SYS_FLASH_CFI=y |
Mario Six | f504d1a | 2018-04-27 14:52:21 +0200 | [diff] [blame] | 99 | CONFIG_PHY_MARVELL=y |
Mario Six | da4fc93 | 2018-03-28 14:38:18 +0200 | [diff] [blame] | 100 | CONFIG_TSEC_ENET=y |
Thomas Chou | a6cec01 | 2015-11-19 21:48:14 +0800 | [diff] [blame] | 101 | CONFIG_SYS_NS16550=y |
Simon Glass | a66c541 | 2016-02-22 22:55:42 -0700 | [diff] [blame] | 102 | CONFIG_OF_LIBFDT=y |
Mario Six | 1faf95d | 2019-01-21 09:18:03 +0100 | [diff] [blame] | 103 | CONFIG_ELBC_BR0_OR0=y |
| 104 | CONFIG_BR0_OR0_NAME="FLASH" |
| 105 | CONFIG_BR0_OR0_BASE=0xFE000000 |
| 106 | CONFIG_BR0_MACHINE_GPCM=y |
| 107 | CONFIG_BR0_PORTSIZE_16BIT=y |
| 108 | CONFIG_OR0_AM_32_MBYTES=y |
| 109 | CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y |
| 110 | CONFIG_OR0_CSNT_EARLIER=y |
| 111 | CONFIG_OR0_EAD_EXTRA=y |
| 112 | CONFIG_OR0_SCY_5=y |
| 113 | CONFIG_OR0_TRLX_RELAXED=y |
| 114 | CONFIG_ELBC_BR1_OR1=y |
| 115 | CONFIG_BR1_OR1_NAME="NAND" |
| 116 | CONFIG_BR1_OR1_BASE=0x61000000 |
| 117 | CONFIG_BR1_ERRORCHECKING_BOTH=y |
| 118 | CONFIG_BR1_MACHINE_FCM=y |
| 119 | CONFIG_BR1_PORTSIZE_8BIT=y |
| 120 | CONFIG_OR1_AM_32_KBYTES=y |
| 121 | CONFIG_OR1_BCTLD_NOT_ASSERTED=y |
| 122 | CONFIG_OR1_RST_ONE_CLOCK=y |
| 123 | CONFIG_OR1_SCY_2=y |
| 124 | CONFIG_OR1_TRLX_RELAXED=y |
| 125 | CONFIG_OR1_CHT_TWO_CLOCK=y |
| 126 | CONFIG_ELBC_BR2_OR2=y |
| 127 | CONFIG_BR2_OR2_NAME="NVRAM" |
| 128 | CONFIG_BR2_OR2_BASE=0x60000000 |
| 129 | CONFIG_BR2_PORTSIZE_8BIT=y |
| 130 | CONFIG_OR2_AM_128_KBYTES=y |
| 131 | CONFIG_OR2_CSNT_EARLIER=y |
| 132 | CONFIG_OR2_EAD_EXTRA=y |
| 133 | CONFIG_OR2_SCY_3=y |
| 134 | CONFIG_OR2_XACS_EXTENDED=y |
| 135 | CONFIG_OR2_TRLX_RELAXED=y |
| 136 | CONFIG_OR2_EHTR_8_CYCLE=y |
| 137 | CONFIG_ELBC_BR3_OR3=y |
| 138 | CONFIG_BR3_OR3_NAME="SRAM" |
| 139 | CONFIG_BR3_OR3_BASE=0x62000000 |
| 140 | CONFIG_BR3_PORTSIZE_16BIT=y |
| 141 | CONFIG_OR3_AM_32_MBYTES=y |
| 142 | CONFIG_OR3_CSNT_EARLIER=y |
| 143 | CONFIG_OR3_EAD_EXTRA=y |
| 144 | CONFIG_OR3_SCY_15=y |
| 145 | CONFIG_OR3_XACS_EXTENDED=y |
| 146 | CONFIG_OR3_TRLX_RELAXED=y |
| 147 | CONFIG_OR3_EHTR_8_CYCLE=y |