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Simon Glassb2c1cac2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay23aee612020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +01005#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -04006#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05307#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +01008
Simon Glassb2c1cac2014-02-26 15:59:21 -07009/ {
10 model = "sandbox";
11 compatible = "sandbox";
12 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060013 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070014
Simon Glassfef72b72014-07-23 06:55:03 -060015 aliases {
16 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -060017 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -070018 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -060019 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060020 gpio1 = &gpio_a;
21 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010022 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070023 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060024 mmc0 = "/mmc0";
25 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070026 pci0 = &pci0;
27 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070028 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020029 remoteproc0 = &rproc_1;
30 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060031 rtc0 = &rtc_0;
32 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060033 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020034 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070035 testbus3 = "/some-bus";
36 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070037 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070038 testfdt3 = "/b-test";
39 testfdt5 = "/some-bus/c-test@5";
40 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070041 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020042 fdt-dummy0 = "/translation-test@8000/dev@0,0";
43 fdt-dummy1 = "/translation-test@8000/dev@1,100";
44 fdt-dummy2 = "/translation-test@8000/dev@2,200";
45 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Dario Binacchib574d682020-12-30 00:16:21 +010046 fdt-dummy4 = "/translation-test@8000/xlatebus@4,400/devs/dev@19";
Simon Glass31680482015-03-25 12:23:05 -060047 usb0 = &usb_0;
48 usb1 = &usb_1;
49 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020050 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020051 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060052 };
53
Simon Glassed96cde2018-12-10 10:37:33 -070054 audio: audio-codec {
55 compatible = "sandbox,audio-codec";
56 #sound-dai-cells = <1>;
57 };
58
Philippe Reynes1ee26482020-07-24 18:19:51 +020059 buttons {
60 compatible = "gpio-keys";
61
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020062 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +020063 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020064 label = "button1";
Philippe Reynes1ee26482020-07-24 18:19:51 +020065 };
66
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020067 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +020068 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020069 label = "button2";
Philippe Reynes1ee26482020-07-24 18:19:51 +020070 };
71 };
72
Marek Szyprowskiad398592021-02-18 11:33:18 +010073 buttons2 {
74 compatible = "adc-keys";
75 io-channels = <&adc 3>;
76 keyup-threshold-microvolt = <3000000>;
77
78 button-up {
79 label = "button3";
80 linux,code = <KEY_F3>;
81 press-threshold-microvolt = <1500000>;
82 };
83
84 button-down {
85 label = "button4";
86 linux,code = <KEY_F4>;
87 press-threshold-microvolt = <1000000>;
88 };
89
90 button-enter {
91 label = "button5";
92 linux,code = <KEY_F5>;
93 press-threshold-microvolt = <500000>;
94 };
95 };
96
Simon Glassc953aaf2018-12-10 10:37:34 -070097 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -060098 reg = <0 0>;
99 compatible = "google,cros-ec-sandbox";
100
101 /*
102 * This describes the flash memory within the EC. Note
103 * that the STM32L flash erases to 0, not 0xff.
104 */
105 flash {
106 image-pos = <0x08000000>;
107 size = <0x20000>;
108 erase-value = <0>;
109
110 /* Information for sandbox */
111 ro {
112 image-pos = <0>;
113 size = <0xf000>;
114 };
115 wp-ro {
116 image-pos = <0xf000>;
117 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700118 used = <0x884>;
119 compress = "lz4";
120 uncomp-size = <0xcf8>;
121 hash {
122 algo = "sha256";
123 value = [00 01 02 03 04 05 06 07
124 08 09 0a 0b 0c 0d 0e 0f
125 10 11 12 13 14 15 16 17
126 18 19 1a 1b 1c 1d 1e 1f];
127 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600128 };
129 rw {
130 image-pos = <0x10000>;
131 size = <0x10000>;
132 };
133 };
134 };
135
Yannick Fertré9712c822019-10-07 15:29:05 +0200136 dsi_host: dsi_host {
137 compatible = "sandbox,dsi-host";
138 };
139
Simon Glassb2c1cac2014-02-26 15:59:21 -0700140 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600141 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700142 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600143 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700144 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600145 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100146 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
147 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700148 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100149 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
150 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
151 <&gpio_b 7 GPIO_IN 3 2 1>,
152 <&gpio_b 8 GPIO_OUT 3 2 1>,
153 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100154 test3-gpios =
155 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
156 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
157 <&gpio_c 2 GPIO_OUT>,
158 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
159 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200160 <&gpio_c 5 GPIO_IN>,
161 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
162 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530163 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
164 test5-gpios = <&gpio_a 19>;
165
Simon Glass6df01f92018-12-10 10:37:37 -0700166 int-value = <1234>;
167 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200168 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200169 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600170 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700171 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600172 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200173 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530174
175 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
176 <&muxcontroller0 2>, <&muxcontroller0 3>,
177 <&muxcontroller1>;
178 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
179 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100180 display-timings {
181 timing0: 240x320 {
182 clock-frequency = <6500000>;
183 hactive = <240>;
184 vactive = <320>;
185 hfront-porch = <6>;
186 hback-porch = <7>;
187 hsync-len = <1>;
188 vback-porch = <5>;
189 vfront-porch = <8>;
190 vsync-len = <2>;
191 hsync-active = <1>;
192 vsync-active = <0>;
193 de-active = <1>;
194 pixelclk-active = <1>;
195 interlaced;
196 doublescan;
197 doubleclk;
198 };
199 timing1: 480x800 {
200 clock-frequency = <9000000>;
201 hactive = <480>;
202 vactive = <800>;
203 hfront-porch = <10>;
204 hback-porch = <59>;
205 hsync-len = <12>;
206 vback-porch = <15>;
207 vfront-porch = <17>;
208 vsync-len = <16>;
209 hsync-active = <0>;
210 vsync-active = <1>;
211 de-active = <0>;
212 pixelclk-active = <0>;
213 };
214 timing2: 800x480 {
215 clock-frequency = <33500000>;
216 hactive = <800>;
217 vactive = <480>;
218 hback-porch = <89>;
219 hfront-porch = <164>;
220 vback-porch = <23>;
221 vfront-porch = <10>;
222 hsync-len = <11>;
223 vsync-len = <13>;
224 };
225 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700226 };
227
228 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600229 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700230 compatible = "not,compatible";
231 };
232
233 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600234 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700235 };
236
Simon Glass5620cf82018-10-01 12:22:40 -0600237 backlight: backlight {
238 compatible = "pwm-backlight";
239 enable-gpios = <&gpio_a 1>;
240 power-supply = <&ldo_1>;
241 pwms = <&pwm 0 1000>;
242 default-brightness-level = <5>;
243 brightness-levels = <0 16 32 64 128 170 202 234 255>;
244 };
245
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200246 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200247 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200248 bind-test-child1 {
249 compatible = "sandbox,phy";
250 #phy-cells = <1>;
251 };
252
253 bind-test-child2 {
254 compatible = "simple-bus";
255 };
256 };
257
Simon Glassb2c1cac2014-02-26 15:59:21 -0700258 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600259 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700260 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600261 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700262 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530263
264 mux-controls = <&muxcontroller0 0>;
265 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700266 };
267
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200268 phy_provider0: gen_phy@0 {
269 compatible = "sandbox,phy";
270 #phy-cells = <1>;
271 };
272
273 phy_provider1: gen_phy@1 {
274 compatible = "sandbox,phy";
275 #phy-cells = <0>;
276 broken;
277 };
278
developer71092972020-05-02 11:35:12 +0200279 phy_provider2: gen_phy@2 {
280 compatible = "sandbox,phy";
281 #phy-cells = <0>;
282 };
283
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200284 gen_phy_user: gen_phy_user {
285 compatible = "simple-bus";
286 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
287 phy-names = "phy1", "phy2", "phy3";
288 };
289
developer71092972020-05-02 11:35:12 +0200290 gen_phy_user1: gen_phy_user1 {
291 compatible = "simple-bus";
292 phys = <&phy_provider0 0>, <&phy_provider2>;
293 phy-names = "phy1", "phy2";
294 };
295
Simon Glassb2c1cac2014-02-26 15:59:21 -0700296 some-bus {
297 #address-cells = <1>;
298 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600299 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600300 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600301 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700302 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600303 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700304 compatible = "denx,u-boot-fdt-test";
305 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600306 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700307 ping-add = <5>;
308 };
Simon Glass40717422014-07-23 06:55:18 -0600309 c-test@0 {
310 compatible = "denx,u-boot-fdt-test";
311 reg = <0>;
312 ping-expect = <6>;
313 ping-add = <6>;
314 };
315 c-test@1 {
316 compatible = "denx,u-boot-fdt-test";
317 reg = <1>;
318 ping-expect = <7>;
319 ping-add = <7>;
320 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700321 };
322
323 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600324 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600325 ping-expect = <6>;
326 ping-add = <6>;
327 compatible = "google,another-fdt-test";
328 };
329
330 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600331 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600332 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700333 ping-add = <6>;
334 compatible = "google,another-fdt-test";
335 };
336
Simon Glass0ccb0972015-01-25 08:27:05 -0700337 f-test {
338 compatible = "denx,u-boot-fdt-test";
339 };
340
341 g-test {
342 compatible = "denx,u-boot-fdt-test";
343 };
344
Bin Mengd9d24782018-10-10 22:07:01 -0700345 h-test {
346 compatible = "denx,u-boot-fdt-test1";
347 };
348
developercf8bc132020-05-02 11:35:10 +0200349 i-test {
350 compatible = "mediatek,u-boot-fdt-test";
351 #address-cells = <1>;
352 #size-cells = <0>;
353
354 subnode@0 {
355 reg = <0>;
356 };
357
358 subnode@1 {
359 reg = <1>;
360 };
361
362 subnode@2 {
363 reg = <2>;
364 };
365 };
366
Simon Glass204675c2019-12-29 21:19:25 -0700367 devres-test {
368 compatible = "denx,u-boot-devres-test";
369 };
370
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530371 another-test {
372 reg = <0 2>;
373 compatible = "denx,u-boot-fdt-test";
374 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
375 test5-gpios = <&gpio_a 19>;
376 };
377
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100378 mmio-bus@0 {
379 #address-cells = <1>;
380 #size-cells = <1>;
381 compatible = "denx,u-boot-test-bus";
382 dma-ranges = <0x10000000 0x00000000 0x00040000>;
383
384 subnode@0 {
385 compatible = "denx,u-boot-fdt-test";
386 };
387 };
388
389 mmio-bus@1 {
390 #address-cells = <1>;
391 #size-cells = <1>;
392 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100393
394 subnode@0 {
395 compatible = "denx,u-boot-fdt-test";
396 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100397 };
398
Simon Glass3c601b12020-07-07 13:12:06 -0600399 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600400 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600401 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600402 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600403 child {
404 compatible = "denx,u-boot-acpi-test";
405 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600406 };
407
Simon Glass3c601b12020-07-07 13:12:06 -0600408 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600409 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600410 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600411 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600412 };
413
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200414 clocks {
415 clk_fixed: clk-fixed {
416 compatible = "fixed-clock";
417 #clock-cells = <0>;
418 clock-frequency = <1234>;
419 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000420
421 clk_fixed_factor: clk-fixed-factor {
422 compatible = "fixed-factor-clock";
423 #clock-cells = <0>;
424 clock-div = <3>;
425 clock-mult = <2>;
426 clocks = <&clk_fixed>;
427 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200428
429 osc {
430 compatible = "fixed-clock";
431 #clock-cells = <0>;
432 clock-frequency = <20000000>;
433 };
Stephen Warrena9622432016-06-17 09:44:00 -0600434 };
435
436 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600437 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600438 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200439 assigned-clocks = <&clk_sandbox 3>;
440 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600441 };
442
443 clk-test {
444 compatible = "sandbox,clk-test";
445 clocks = <&clk_fixed>,
446 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200447 <&clk_sandbox 0>,
448 <&clk_sandbox 3>,
449 <&clk_sandbox 2>;
450 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600451 };
452
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200453 ccf: clk-ccf {
454 compatible = "sandbox,clk-ccf";
455 };
456
Simon Glass5b968632015-05-22 15:42:15 -0600457 eth@10002000 {
458 compatible = "sandbox,eth";
459 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500460 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600461 };
462
463 eth_5: eth@10003000 {
464 compatible = "sandbox,eth";
465 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500466 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600467 };
468
Bin Meng04a11cb2015-08-27 22:25:53 -0700469 eth_3: sbe5 {
470 compatible = "sandbox,eth";
471 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500472 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700473 };
474
Simon Glass5b968632015-05-22 15:42:15 -0600475 eth@10004000 {
476 compatible = "sandbox,eth";
477 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500478 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600479 };
480
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700481 firmware {
482 sandbox_firmware: sandbox-firmware {
483 compatible = "sandbox,firmware";
484 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200485
486 sandbox-scmi-agent@0 {
487 compatible = "sandbox,scmi-agent";
488 #address-cells = <1>;
489 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200490
491 clk_scmi0: protocol@14 {
492 reg = <0x14>;
493 #clock-cells = <1>;
494 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200495
496 reset_scmi0: protocol@16 {
497 reg = <0x16>;
498 #reset-cells = <1>;
499 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200500 };
501
502 sandbox-scmi-agent@1 {
503 compatible = "sandbox,scmi-agent";
504 #address-cells = <1>;
505 #size-cells = <0>;
506
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200507 clk_scmi1: protocol@14 {
508 reg = <0x14>;
509 #clock-cells = <1>;
510 };
511
Etienne Carriere02fd1262020-09-09 18:44:00 +0200512 protocol@10 {
513 reg = <0x10>;
514 };
515 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700516 };
517
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100518 pinctrl-gpio {
519 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700520
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100521 gpio_a: base-gpios {
522 compatible = "sandbox,gpio";
523 gpio-controller;
524 #gpio-cells = <1>;
525 gpio-bank-name = "a";
526 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200527 hog_input_active_low {
528 gpio-hog;
529 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200530 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200531 };
532 hog_input_active_high {
533 gpio-hog;
534 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200535 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200536 };
537 hog_output_low {
538 gpio-hog;
539 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200540 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200541 };
542 hog_output_high {
543 gpio-hog;
544 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200545 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200546 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100547 };
548
549 gpio_b: extra-gpios {
550 compatible = "sandbox,gpio";
551 gpio-controller;
552 #gpio-cells = <5>;
553 gpio-bank-name = "b";
554 sandbox,gpio-count = <10>;
555 };
Simon Glass25348a42014-10-13 23:42:11 -0600556
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100557 gpio_c: pinmux-gpios {
558 compatible = "sandbox,gpio";
559 gpio-controller;
560 #gpio-cells = <2>;
561 gpio-bank-name = "c";
562 sandbox,gpio-count = <10>;
563 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100564 };
565
Simon Glass7df766e2014-12-10 08:55:55 -0700566 i2c@0 {
567 #address-cells = <1>;
568 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600569 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700570 compatible = "sandbox,i2c";
571 clock-frequency = <100000>;
572 eeprom@2c {
573 reg = <0x2c>;
574 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700575 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200576 partitions {
577 compatible = "fixed-partitions";
578 #address-cells = <1>;
579 #size-cells = <1>;
580 bootcount_i2c: bootcount@10 {
581 reg = <10 2>;
582 };
583 };
Simon Glass7df766e2014-12-10 08:55:55 -0700584 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200585
Simon Glass336b2952015-05-22 15:42:17 -0600586 rtc_0: rtc@43 {
587 reg = <0x43>;
588 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700589 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600590 };
591
592 rtc_1: rtc@61 {
593 reg = <0x61>;
594 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700595 sandbox,emul = <&emul1>;
596 };
597
598 i2c_emul: emul {
599 reg = <0xff>;
600 compatible = "sandbox,i2c-emul-parent";
601 emul_eeprom: emul-eeprom {
602 compatible = "sandbox,i2c-eeprom";
603 sandbox,filename = "i2c.bin";
604 sandbox,size = <256>;
605 };
606 emul0: emul0 {
607 compatible = "sandbox,i2c-rtc";
608 };
609 emul1: emull {
Simon Glass336b2952015-05-22 15:42:17 -0600610 compatible = "sandbox,i2c-rtc";
611 };
612 };
613
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200614 sandbox_pmic: sandbox_pmic {
615 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700616 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200617 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200618
619 mc34708: pmic@41 {
620 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700621 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200622 };
Simon Glass7df766e2014-12-10 08:55:55 -0700623 };
624
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100625 bootcount@0 {
626 compatible = "u-boot,bootcount-rtc";
627 rtc = <&rtc_1>;
628 offset = <0x13>;
629 };
630
Michal Simek4f18f922020-05-28 11:48:55 +0200631 bootcount {
632 compatible = "u-boot,bootcount-i2c-eeprom";
633 i2c-eeprom = <&bootcount_i2c>;
634 };
635
Marek Szyprowskiad398592021-02-18 11:33:18 +0100636 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100637 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100638 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100639 vdd-supply = <&buck2>;
640 vss-microvolts = <0>;
641 };
642
Simon Glass515dcff2020-02-06 09:55:00 -0700643 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700644 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700645 interrupt-controller;
646 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700647 };
648
Simon Glass90b6fef2016-01-18 19:52:26 -0700649 lcd {
650 u-boot,dm-pre-reloc;
651 compatible = "sandbox,lcd-sdl";
652 xres = <1366>;
653 yres = <768>;
654 };
655
Simon Glassd783eb32015-07-06 12:54:34 -0600656 leds {
657 compatible = "gpio-leds";
658
659 iracibble {
660 gpios = <&gpio_a 1 0>;
661 label = "sandbox:red";
662 };
663
664 martinet {
665 gpios = <&gpio_a 2 0>;
666 label = "sandbox:green";
667 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200668
669 default_on {
670 gpios = <&gpio_a 5 0>;
671 label = "sandbox:default_on";
672 default-state = "on";
673 };
674
675 default_off {
676 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400677 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200678 default-state = "off";
679 };
Simon Glassd783eb32015-07-06 12:54:34 -0600680 };
681
Stephen Warren62f2c902016-05-16 17:41:37 -0600682 mbox: mbox {
683 compatible = "sandbox,mbox";
684 #mbox-cells = <1>;
685 };
686
687 mbox-test {
688 compatible = "sandbox,mbox-test";
689 mboxes = <&mbox 100>, <&mbox 1>;
690 mbox-names = "other", "test";
691 };
692
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900693 cpus {
Sean Anderson79d3bba2020-09-28 10:52:23 -0400694 timebase-frequency = <2000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900695 cpu-test1 {
Sean Anderson79d3bba2020-09-28 10:52:23 -0400696 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900697 compatible = "sandbox,cpu_sandbox";
698 u-boot,dm-pre-reloc;
699 };
Mario Sixdea5df72018-08-06 10:23:44 +0200700
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900701 cpu-test2 {
702 compatible = "sandbox,cpu_sandbox";
703 u-boot,dm-pre-reloc;
704 };
Mario Sixdea5df72018-08-06 10:23:44 +0200705
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900706 cpu-test3 {
707 compatible = "sandbox,cpu_sandbox";
708 u-boot,dm-pre-reloc;
709 };
Mario Sixdea5df72018-08-06 10:23:44 +0200710 };
711
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500712 chipid: chipid {
713 compatible = "sandbox,soc";
714 };
715
Simon Glassc953aaf2018-12-10 10:37:34 -0700716 i2s: i2s {
717 compatible = "sandbox,i2s";
718 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700719 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700720 };
721
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200722 nop-test_0 {
723 compatible = "sandbox,nop_sandbox1";
724 nop-test_1 {
725 compatible = "sandbox,nop_sandbox2";
726 bind = "True";
727 };
728 nop-test_2 {
729 compatible = "sandbox,nop_sandbox2";
730 bind = "False";
731 };
732 };
733
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200734 misc-test {
735 compatible = "sandbox,misc_sandbox";
736 };
737
Simon Glasse4fef742017-04-23 20:02:07 -0600738 mmc2 {
739 compatible = "sandbox,mmc";
740 };
741
742 mmc1 {
743 compatible = "sandbox,mmc";
744 };
745
746 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600747 compatible = "sandbox,mmc";
748 };
749
Simon Glass53a68b32019-02-16 20:24:50 -0700750 pch {
751 compatible = "sandbox,pch";
752 };
753
Tom Rini4a3ca482020-02-11 12:41:23 -0500754 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700755 compatible = "sandbox,pci";
756 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500757 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700758 #address-cells = <3>;
759 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600760 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700761 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700762 pci@0,0 {
763 compatible = "pci-generic";
764 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600765 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700766 };
Alex Margineanf1274432019-06-07 11:24:24 +0300767 pci@1,0 {
768 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600769 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
770 reg = <0x02000814 0 0 0 0
771 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600772 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300773 };
Simon Glass937bb472019-12-06 21:41:57 -0700774 p2sb-pci@2,0 {
775 compatible = "sandbox,p2sb";
776 reg = <0x02001010 0 0 0 0>;
777 sandbox,emul = <&p2sb_emul>;
778
779 adder {
780 intel,p2sb-port-id = <3>;
781 compatible = "sandbox,adder";
782 };
783 };
Simon Glass8c501022019-12-06 21:41:54 -0700784 pci@1e,0 {
785 compatible = "sandbox,pmc";
786 reg = <0xf000 0 0 0 0>;
787 sandbox,emul = <&pmc_emul1e>;
788 acpi-base = <0x400>;
789 gpe0-dwx-mask = <0xf>;
790 gpe0-dwx-shift-base = <4>;
791 gpe0-dw = <6 7 9>;
792 gpe0-sts = <0x20>;
793 gpe0-en = <0x30>;
794 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700795 pci@1f,0 {
796 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600797 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
798 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600799 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700800 };
801 };
802
Simon Glassb98ba4c2019-09-25 08:56:10 -0600803 pci-emul0 {
804 compatible = "sandbox,pci-emul-parent";
805 swap_case_emul0_0: emul0@0,0 {
806 compatible = "sandbox,swap-case";
807 };
808 swap_case_emul0_1: emul0@1,0 {
809 compatible = "sandbox,swap-case";
810 use-ea;
811 };
812 swap_case_emul0_1f: emul0@1f,0 {
813 compatible = "sandbox,swap-case";
814 };
Simon Glass937bb472019-12-06 21:41:57 -0700815 p2sb_emul: emul@2,0 {
816 compatible = "sandbox,p2sb-emul";
817 };
Simon Glass8c501022019-12-06 21:41:54 -0700818 pmc_emul1e: emul@1e,0 {
819 compatible = "sandbox,pmc-emul";
820 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600821 };
822
Tom Rini4a3ca482020-02-11 12:41:23 -0500823 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700824 compatible = "sandbox,pci";
825 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500826 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700827 #address-cells = <3>;
828 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -0700829 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
830 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
831 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700832 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200833 0x0c 0x00 0x1234 0x5678
834 0x10 0x00 0x1234 0x5678>;
835 pci@10,0 {
836 reg = <0x8000 0 0 0 0>;
837 };
Bin Meng408e5902018-08-03 01:14:41 -0700838 };
839
Tom Rini4a3ca482020-02-11 12:41:23 -0500840 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -0700841 compatible = "sandbox,pci";
842 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500843 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -0700844 #address-cells = <3>;
845 #size-cells = <2>;
846 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
847 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
848 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
849 pci@1f,0 {
850 compatible = "pci-generic";
851 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600852 sandbox,emul = <&swap_case_emul2_1f>;
853 };
854 };
855
856 pci-emul2 {
857 compatible = "sandbox,pci-emul-parent";
858 swap_case_emul2_1f: emul2@1f,0 {
859 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700860 };
861 };
862
Ramon Friedc64f19b2019-04-27 11:15:23 +0300863 pci_ep: pci_ep {
864 compatible = "sandbox,pci_ep";
865 };
866
Simon Glass9c433fe2017-04-23 20:10:44 -0600867 probing {
868 compatible = "simple-bus";
869 test1 {
870 compatible = "denx,u-boot-probe-test";
871 };
872
873 test2 {
874 compatible = "denx,u-boot-probe-test";
875 };
876
877 test3 {
878 compatible = "denx,u-boot-probe-test";
879 };
880
881 test4 {
882 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100883 first-syscon = <&syscon0>;
884 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +0100885 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600886 };
887 };
888
Stephen Warren92c67fa2016-07-13 13:45:31 -0600889 pwrdom: power-domain {
890 compatible = "sandbox,power-domain";
891 #power-domain-cells = <1>;
892 };
893
894 power-domain-test {
895 compatible = "sandbox,power-domain-test";
896 power-domains = <&pwrdom 2>;
897 };
898
Simon Glass5620cf82018-10-01 12:22:40 -0600899 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600900 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600901 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600902 };
903
904 pwm2 {
905 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600906 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600907 };
908
Simon Glass3d355e62015-07-06 12:54:31 -0600909 ram {
910 compatible = "sandbox,ram";
911 };
912
Simon Glassd860f222015-07-06 12:54:29 -0600913 reset@0 {
914 compatible = "sandbox,warm-reset";
915 };
916
917 reset@1 {
918 compatible = "sandbox,reset";
919 };
920
Stephen Warren6488e642016-06-17 09:43:59 -0600921 resetc: reset-ctl {
922 compatible = "sandbox,reset-ctl";
923 #reset-cells = <1>;
924 };
925
926 reset-ctl-test {
927 compatible = "sandbox,reset-ctl-test";
928 resets = <&resetc 100>, <&resetc 2>;
929 reset-names = "other", "test";
930 };
931
Sughosh Ganu23e37512019-12-28 23:58:31 +0530932 rng {
933 compatible = "sandbox,sandbox-rng";
934 };
935
Nishanth Menonedf85812015-09-17 15:42:41 -0500936 rproc_1: rproc@1 {
937 compatible = "sandbox,test-processor";
938 remoteproc-name = "remoteproc-test-dev1";
939 };
940
941 rproc_2: rproc@2 {
942 compatible = "sandbox,test-processor";
943 internal-memory-mapped;
944 remoteproc-name = "remoteproc-test-dev2";
945 };
946
Simon Glass5620cf82018-10-01 12:22:40 -0600947 panel {
948 compatible = "simple-panel";
949 backlight = <&backlight 0 100>;
950 };
951
Ramon Fried26ed32e2018-07-02 02:57:59 +0300952 smem@0 {
953 compatible = "sandbox,smem";
954 };
955
Simon Glass76072ac2018-12-10 10:37:36 -0700956 sound {
957 compatible = "sandbox,sound";
958 cpu {
959 sound-dai = <&i2s 0>;
960 };
961
962 codec {
963 sound-dai = <&audio 0>;
964 };
965 };
966
Simon Glass25348a42014-10-13 23:42:11 -0600967 spi@0 {
968 #address-cells = <1>;
969 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600970 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600971 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +0200972 cs-gpios = <0>, <0>, <&gpio_a 0>;
Simon Glass25348a42014-10-13 23:42:11 -0600973 spi.bin@0 {
974 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000975 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -0600976 spi-max-frequency = <40000000>;
977 sandbox,filename = "spi.bin";
978 };
Ovidiu Panaitae734732020-12-14 19:06:47 +0200979 spi.bin@1 {
980 reg = <1>;
981 compatible = "spansion,m25p16", "jedec,spi-nor";
982 spi-max-frequency = <50000000>;
983 sandbox,filename = "spi.bin";
984 spi-cpol;
985 spi-cpha;
986 };
Simon Glass25348a42014-10-13 23:42:11 -0600987 };
988
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100989 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -0600990 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +0200991 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -0600992 };
993
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100994 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -0600995 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600996 reg = <0x20 5
997 0x28 6
998 0x30 7
999 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001000 };
1001
Patrick Delaunayee010432019-03-07 09:57:13 +01001002 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001003 compatible = "simple-mfd", "syscon";
1004 reg = <0x40 5
1005 0x48 6
1006 0x50 7
1007 0x58 8>;
1008 };
1009
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301010 syscon3: syscon@3 {
1011 compatible = "simple-mfd", "syscon";
1012 reg = <0x000100 0x10>;
1013
1014 muxcontroller0: a-mux-controller {
1015 compatible = "mmio-mux";
1016 #mux-control-cells = <1>;
1017
1018 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1019 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1020 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1021 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1022 u-boot,mux-autoprobe;
1023 };
1024 };
1025
1026 muxcontroller1: emul-mux-controller {
1027 compatible = "mux-emul";
1028 #mux-control-cells = <0>;
1029 u-boot,mux-autoprobe;
1030 idle-state = <0xabcd>;
1031 };
1032
Simon Glass791a17f2020-12-16 21:20:27 -07001033 testfdtm0 {
1034 compatible = "denx,u-boot-fdtm-test";
1035 };
1036
1037 testfdtm1: testfdtm1 {
1038 compatible = "denx,u-boot-fdtm-test";
1039 };
1040
1041 testfdtm2 {
1042 compatible = "denx,u-boot-fdtm-test";
1043 };
1044
Sean Anderson79d3bba2020-09-28 10:52:23 -04001045 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001046 compatible = "sandbox,timer";
1047 clock-frequency = <1000000>;
1048 };
1049
Sean Anderson79d3bba2020-09-28 10:52:23 -04001050 timer@1 {
1051 compatible = "sandbox,timer";
1052 sandbox,timebase-frequency-fallback;
1053 };
1054
Miquel Raynal80938c12018-05-15 11:57:27 +02001055 tpm2 {
1056 compatible = "sandbox,tpm2";
1057 };
1058
Simon Glass5b968632015-05-22 15:42:15 -06001059 uart0: serial {
1060 compatible = "sandbox,serial";
1061 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -05001062 };
1063
Simon Glass31680482015-03-25 12:23:05 -06001064 usb_0: usb@0 {
1065 compatible = "sandbox,usb";
1066 status = "disabled";
1067 hub {
1068 compatible = "sandbox,usb-hub";
1069 #address-cells = <1>;
1070 #size-cells = <0>;
1071 flash-stick {
1072 reg = <0>;
1073 compatible = "sandbox,usb-flash";
1074 };
1075 };
1076 };
1077
1078 usb_1: usb@1 {
1079 compatible = "sandbox,usb";
1080 hub {
1081 compatible = "usb-hub";
1082 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001083 #address-cells = <1>;
1084 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001085 hub-emul {
1086 compatible = "sandbox,usb-hub";
1087 #address-cells = <1>;
1088 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001089 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001090 reg = <0>;
1091 compatible = "sandbox,usb-flash";
1092 sandbox,filepath = "testflash.bin";
1093 };
1094
Simon Glass4700fe52015-11-08 23:48:01 -07001095 flash-stick@1 {
1096 reg = <1>;
1097 compatible = "sandbox,usb-flash";
1098 sandbox,filepath = "testflash1.bin";
1099 };
1100
1101 flash-stick@2 {
1102 reg = <2>;
1103 compatible = "sandbox,usb-flash";
1104 sandbox,filepath = "testflash2.bin";
1105 };
1106
Simon Glassc0ccc722015-11-08 23:48:08 -07001107 keyb@3 {
1108 reg = <3>;
1109 compatible = "sandbox,usb-keyb";
1110 };
1111
Simon Glass31680482015-03-25 12:23:05 -06001112 };
Michael Walle7c961322020-06-02 01:47:07 +02001113
1114 usbstor@1 {
1115 reg = <1>;
1116 };
1117 usbstor@3 {
1118 reg = <3>;
1119 };
Simon Glass31680482015-03-25 12:23:05 -06001120 };
1121 };
1122
1123 usb_2: usb@2 {
1124 compatible = "sandbox,usb";
1125 status = "disabled";
1126 };
1127
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001128 spmi: spmi@0 {
1129 compatible = "sandbox,spmi";
1130 #address-cells = <0x1>;
1131 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001132 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001133 pm8916@0 {
1134 compatible = "qcom,spmi-pmic";
1135 reg = <0x0 0x1>;
1136 #address-cells = <0x1>;
1137 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001138 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001139
1140 spmi_gpios: gpios@c000 {
1141 compatible = "qcom,pm8916-gpio";
1142 reg = <0xc000 0x400>;
1143 gpio-controller;
1144 gpio-count = <4>;
1145 #gpio-cells = <2>;
1146 gpio-bank-name="spmi";
1147 };
1148 };
1149 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001150
1151 wdt0: wdt@0 {
1152 compatible = "sandbox,wdt";
1153 };
Rob Clarka471b672018-01-10 11:33:30 +01001154
Mario Six95922152018-08-09 14:51:19 +02001155 axi: axi@0 {
1156 compatible = "sandbox,axi";
1157 #address-cells = <0x1>;
1158 #size-cells = <0x1>;
1159 store@0 {
1160 compatible = "sandbox,sandbox_store";
1161 reg = <0x0 0x400>;
1162 };
1163 };
1164
Rob Clarka471b672018-01-10 11:33:30 +01001165 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001166 #address-cells = <1>;
1167 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001168 setting = "sunrise ohoka";
1169 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001170 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001171 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001172 chosen-test {
1173 compatible = "denx,u-boot-fdt-test";
1174 reg = <9 1>;
1175 };
1176 };
Mario Six35616ef2018-03-12 14:53:33 +01001177
1178 translation-test@8000 {
1179 compatible = "simple-bus";
1180 reg = <0x8000 0x4000>;
1181
1182 #address-cells = <0x2>;
1183 #size-cells = <0x1>;
1184
1185 ranges = <0 0x0 0x8000 0x1000
1186 1 0x100 0x9000 0x1000
1187 2 0x200 0xA000 0x1000
1188 3 0x300 0xB000 0x1000
Dario Binacchib574d682020-12-30 00:16:21 +01001189 4 0x400 0xC000 0x1000
Mario Six35616ef2018-03-12 14:53:33 +01001190 >;
1191
Fabien Dessenne22236e02019-05-31 15:11:30 +02001192 dma-ranges = <0 0x000 0x10000000 0x1000
1193 1 0x100 0x20000000 0x1000
1194 >;
1195
Mario Six35616ef2018-03-12 14:53:33 +01001196 dev@0,0 {
1197 compatible = "denx,u-boot-fdt-dummy";
1198 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001199 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001200 };
1201
1202 dev@1,100 {
1203 compatible = "denx,u-boot-fdt-dummy";
1204 reg = <1 0x100 0x1000>;
1205
1206 };
1207
1208 dev@2,200 {
1209 compatible = "denx,u-boot-fdt-dummy";
1210 reg = <2 0x200 0x1000>;
1211 };
1212
1213
1214 noxlatebus@3,300 {
1215 compatible = "simple-bus";
1216 reg = <3 0x300 0x1000>;
1217
1218 #address-cells = <0x1>;
1219 #size-cells = <0x0>;
1220
1221 dev@42 {
1222 compatible = "denx,u-boot-fdt-dummy";
1223 reg = <0x42>;
1224 };
1225 };
Dario Binacchib574d682020-12-30 00:16:21 +01001226
1227 xlatebus@4,400 {
1228 compatible = "sandbox,zero-size-cells-bus";
1229 reg = <4 0x400 0x1000>;
1230 #address-cells = <1>;
1231 #size-cells = <1>;
1232 ranges = <0 4 0x400 0x1000>;
1233
1234 devs {
1235 #address-cells = <1>;
1236 #size-cells = <0>;
1237
1238 dev@19 {
1239 compatible = "denx,u-boot-fdt-dummy";
1240 reg = <0x19>;
1241 };
1242 };
1243 };
1244
Mario Six35616ef2018-03-12 14:53:33 +01001245 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001246
1247 osd {
1248 compatible = "sandbox,sandbox_osd";
1249 };
Tom Rinib93eea72018-09-30 18:16:51 -04001250
Jens Wiklander86afaa62018-09-25 16:40:16 +02001251 sandbox_tee {
1252 compatible = "sandbox,tee";
1253 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001254
1255 sandbox_virtio1 {
1256 compatible = "sandbox,virtio1";
1257 };
1258
1259 sandbox_virtio2 {
1260 compatible = "sandbox,virtio2";
1261 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001262
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001263 sandbox_scmi {
1264 compatible = "sandbox,scmi-devices";
1265 clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
Etienne Carriere8b9b6892020-09-09 18:44:07 +02001266 resets = <&reset_scmi0 3>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001267 };
1268
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001269 pinctrl {
1270 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001271
Sean Anderson3438e3b2020-09-14 11:01:57 -04001272 pinctrl-names = "default", "alternate";
1273 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1274 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001275
Sean Anderson3438e3b2020-09-14 11:01:57 -04001276 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001277 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001278 pins = "P5";
1279 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001280 bias-pull-up;
1281 input-disable;
1282 };
1283 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001284 pins = "P6";
1285 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001286 output-high;
1287 drive-open-drain;
1288 };
1289 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001290 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001291 bias-pull-down;
1292 input-enable;
1293 };
1294 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001295 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001296 bias-disable;
1297 };
1298 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001299
1300 pinctrl_i2c: i2c {
1301 groups {
1302 groups = "I2C_UART";
1303 function = "I2C";
1304 };
1305
1306 pins {
1307 pins = "P0", "P1";
1308 drive-open-drain;
1309 };
1310 };
1311
1312 pinctrl_i2s: i2s {
1313 groups = "SPI_I2S";
1314 function = "I2S";
1315 };
1316
1317 pinctrl_spi: spi {
1318 groups = "SPI_I2S";
1319 function = "SPI";
1320
1321 cs {
1322 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1323 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1324 };
1325 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001326 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001327
1328 hwspinlock@0 {
1329 compatible = "sandbox,hwspinlock";
1330 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001331
1332 dma: dma {
1333 compatible = "sandbox,dma";
1334 #dma-cells = <1>;
1335
1336 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1337 dma-names = "m2m", "tx0", "rx0";
1338 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001339
Alex Marginean0649be52019-07-12 10:13:53 +03001340 /*
1341 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1342 * end of the test. If parent mdio is removed first, clean-up of the
1343 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1344 * active at the end of the test. That it turn doesn't allow the mdio
1345 * class to be destroyed, triggering an error.
1346 */
1347 mdio-mux-test {
1348 compatible = "sandbox,mdio-mux";
1349 #address-cells = <1>;
1350 #size-cells = <0>;
1351 mdio-parent-bus = <&mdio>;
1352
1353 mdio-ch-test@0 {
1354 reg = <0>;
1355 };
1356 mdio-ch-test@1 {
1357 reg = <1>;
1358 };
1359 };
1360
1361 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001362 compatible = "sandbox,mdio";
1363 };
Sean Andersonb7860542020-06-24 06:41:12 -04001364
1365 pm-bus-test {
1366 compatible = "simple-pm-bus";
1367 clocks = <&clk_sandbox 4>;
1368 power-domains = <&pwrdom 1>;
1369 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001370
1371 resetc2: syscon-reset {
1372 compatible = "syscon-reset";
1373 #reset-cells = <1>;
1374 regmap = <&syscon0>;
1375 offset = <1>;
1376 mask = <0x27FFFFFF>;
1377 assert-high = <0>;
1378 };
1379
1380 syscon-reset-test {
1381 compatible = "sandbox,misc_sandbox";
1382 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1383 reset-names = "valid", "no_mask", "out_of_range";
1384 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301385
Simon Glass458b66a2020-11-05 06:32:05 -07001386 sysinfo {
1387 compatible = "sandbox,sysinfo-sandbox";
1388 };
1389
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301390 some_regmapped-bus {
1391 #address-cells = <0x1>;
1392 #size-cells = <0x1>;
1393
1394 ranges = <0x0 0x0 0x10>;
1395 compatible = "simple-bus";
1396
1397 regmap-test_0 {
1398 reg = <0 0x10>;
1399 compatible = "sandbox,regmap_test";
1400 };
1401 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001402};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001403
1404#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001405#include "cros-ec-keyboard.dtsi"