Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 989f24f0ec43feb7b235d200d96dc5177e9dc355 / . / arch / arm / include / asm / arch-rockchip / cru_px30.h
blob: 798444ae49f5d2d7aefc9d8bb12388f9a0badc8f [file] [log] [blame]
Kever Yangba1033d2019-07-11 10:42:16 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
4 */
5#ifndef _ASM_ARCH_CRU_PX30_H
6#define _ASM_ARCH_CRU_PX30_H
7
8#include <common.h>
9
10#define MHz 1000000
11#define KHz 1000
12#define OSC_HZ (24 * MHz)
13
14#define APLL_HZ (600 * MHz)
15#define GPLL_HZ (1200 * MHz)
16#define NPLL_HZ (1188 * MHz)
17#define ACLK_BUS_HZ (200 * MHz)
18#define HCLK_BUS_HZ (150 * MHz)
19#define PCLK_BUS_HZ (100 * MHz)
20#define ACLK_PERI_HZ (200 * MHz)
21#define HCLK_PERI_HZ (150 * MHz)
22#define PCLK_PMU_HZ (100 * MHz)
23
24/* PX30 pll id */
25enum px30_pll_id {
26 APLL,
27 DPLL,
28 CPLL,
29 NPLL,
30 GPLL,
31 PLL_COUNT,
32};
33
34struct px30_clk_priv {
35 struct px30_cru *cru;
36 ulong gpll_hz;
37};
38
39struct px30_pmuclk_priv {
40 struct px30_pmucru *pmucru;
41 ulong gpll_hz;
42};
43
44struct px30_pll {
45 unsigned int con0;
46 unsigned int con1;
47 unsigned int con2;
48 unsigned int con3;
49 unsigned int con4;
50 unsigned int reserved0[3];
51};
52
53struct px30_cru {
54 struct px30_pll pll[4];
55 unsigned int reserved1[8];
56 unsigned int mode;
57 unsigned int misc;
58 unsigned int reserved2[2];
59 unsigned int glb_cnt_th;
60 unsigned int glb_rst_st;
61 unsigned int glb_srst_fst;
62 unsigned int glb_srst_snd;
63 unsigned int glb_rst_con;
64 unsigned int reserved3[7];
65 unsigned int hwffc_con0;
66 unsigned int reserved4;
67 unsigned int hwffc_th;
68 unsigned int hwffc_intst;
69 unsigned int apll_con0_s;
70 unsigned int apll_con1_s;
71 unsigned int clksel_con0_s;
72 unsigned int reserved5;
73 unsigned int clksel_con[60];
74 unsigned int reserved6[4];
75 unsigned int clkgate_con[18];
76 unsigned int reserved7[(0x280 - 0x244) / 4 - 1];
77 unsigned int ssgtbl[32];
78 unsigned int softrst_con[12];
79 unsigned int reserved8[(0x380 - 0x32c) / 4 - 1];
80 unsigned int sdmmc_con[2];
81 unsigned int sdio_con[2];
82 unsigned int emmc_con[2];
83 unsigned int reserved9[(0x400 - 0x394) / 4 - 1];
84 unsigned int autocs_con[8];
85};
86
87check_member(px30_cru, autocs_con[7], 0x41c);
88
89struct px30_pmucru {
90 struct px30_pll pll;
91 unsigned int pmu_mode;
92 unsigned int reserved1[7];
93 unsigned int pmu_clksel_con[6];
94 unsigned int reserved2[10];
95 unsigned int pmu_clkgate_con[2];
96 unsigned int reserved3[14];
97 unsigned int pmu_autocs_con[2];
98};
99
100check_member(px30_pmucru, pmu_autocs_con[1], 0xc4);
101
102struct pll_rate_table {
103 unsigned long rate;
104 unsigned int fbdiv;
105 unsigned int postdiv1;
106 unsigned int refdiv;
107 unsigned int postdiv2;
108 unsigned int dsmpd;
109 unsigned int frac;
110};
111
112struct cpu_rate_table {
113 unsigned long rate;
114 unsigned int aclk_div;
115 unsigned int pclk_div;
116};
117
118enum {
119 /* PLLCON0*/
120 PLL_BP_SHIFT = 15,
121 PLL_POSTDIV1_SHIFT = 12,
122 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
123 PLL_FBDIV_SHIFT = 0,
124 PLL_FBDIV_MASK = 0xfff,
125
126 /* PLLCON1 */
127 PLL_PDSEL_SHIFT = 15,
128 PLL_PD1_SHIFT = 14,
129 PLL_PD_SHIFT = 13,
130 PLL_PD_MASK = 1 << PLL_PD_SHIFT,
131 PLL_DSMPD_SHIFT = 12,
132 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
133 PLL_LOCK_STATUS_SHIFT = 10,
134 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
135 PLL_POSTDIV2_SHIFT = 6,
136 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
137 PLL_REFDIV_SHIFT = 0,
138 PLL_REFDIV_MASK = 0x3f,
139
140 /* PLLCON2 */
141 PLL_FOUT4PHASEPD_SHIFT = 27,
142 PLL_FOUTVCOPD_SHIFT = 26,
143 PLL_FOUTPOSTDIVPD_SHIFT = 25,
144 PLL_DACPD_SHIFT = 24,
145 PLL_FRAC_DIV = 0xffffff,
146
147 /* CRU_MODE */
148 PLLMUX_FROM_XIN24M = 0,
149 PLLMUX_FROM_PLL,
150 PLLMUX_FROM_RTC32K,
151 USBPHY480M_MODE_SHIFT = 8,
152 USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT,
153 NPLL_MODE_SHIFT = 6,
154 NPLL_MODE_MASK = 3 << NPLL_MODE_SHIFT,
155 DPLL_MODE_SHIFT = 4,
156 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT,
157 CPLL_MODE_SHIFT = 2,
158 CPLL_MODE_MASK = 3 << CPLL_MODE_SHIFT,
159 APLL_MODE_SHIFT = 0,
160 APLL_MODE_MASK = 3 << APLL_MODE_SHIFT,
161
162 /* CRU_CLK_SEL0_CON */
163 CORE_ACLK_DIV_SHIFT = 12,
164 CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT,
165 CORE_DBG_DIV_SHIFT = 8,
166 CORE_DBG_DIV_MASK = 0x03 << CORE_DBG_DIV_SHIFT,
167 CORE_CLK_PLL_SEL_SHIFT = 7,
168 CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT,
169 CORE_CLK_PLL_SEL_APLL = 0,
170 CORE_CLK_PLL_SEL_GPLL,
171 CORE_DIV_CON_SHIFT = 0,
172 CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT,
173
174 /* CRU_CLK_SEL3_CON */
175 ACLK_VO_PLL_SHIFT = 6,
176 ACLK_VO_PLL_MASK = 0x3 << ACLK_VO_PLL_SHIFT,
177 ACLK_VO_SEL_GPLL = 0,
178 ACLK_VO_SEL_CPLL,
179 ACLK_VO_SEL_NPLL,
180 ACLK_VO_DIV_SHIFT = 0,
181 ACLK_VO_DIV_MASK = 0x1f << ACLK_VO_DIV_SHIFT,
182
183 /* CRU_CLK_SEL5_CON */
184 DCLK_VOPB_SEL_SHIFT = 14,
185 DCLK_VOPB_SEL_MASK = 0x3 << DCLK_VOPB_SEL_SHIFT,
186 DCLK_VOPB_SEL_DIVOUT = 0,
187 DCLK_VOPB_SEL_FRACOUT,
188 DCLK_VOPB_SEL_24M,
189 DCLK_VOPB_PLL_SEL_SHIFT = 11,
190 DCLK_VOPB_PLL_SEL_MASK = 0x1 << DCLK_VOPB_PLL_SEL_SHIFT,
191 DCLK_VOPB_PLL_SEL_CPLL = 0,
192 DCLK_VOPB_PLL_SEL_NPLL,
193 DCLK_VOPB_DIV_SHIFT = 0,
194 DCLK_VOPB_DIV_MASK = 0xff,
195
196 /* CRU_CLK_SEL8_CON */
197 DCLK_VOPL_SEL_SHIFT = 14,
198 DCLK_VOPL_SEL_MASK = 0x3 << DCLK_VOPL_SEL_SHIFT,
199 DCLK_VOPL_SEL_DIVOUT = 0,
200 DCLK_VOPL_SEL_FRACOUT,
201 DCLK_VOPL_SEL_24M,
202 DCLK_VOPL_PLL_SEL_SHIFT = 11,
203 DCLK_VOPL_PLL_SEL_MASK = 0x1 << DCLK_VOPL_PLL_SEL_SHIFT,
204 DCLK_VOPL_PLL_SEL_NPLL = 0,
205 DCLK_VOPL_PLL_SEL_CPLL,
206 DCLK_VOPL_DIV_SHIFT = 0,
207 DCLK_VOPL_DIV_MASK = 0xff,
208
209 /* CRU_CLK_SEL14_CON */
210 PERI_PLL_SEL_SHIFT = 15,
211 PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT,
212 PERI_PLL_GPLL = 0,
213 PERI_PLL_CPLL,
214 PERI_HCLK_DIV_SHIFT = 8,
215 PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT,
216 PERI_ACLK_DIV_SHIFT = 0,
217 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
218
219 /* CRU_CLKSEL15_CON */
220 NANDC_CLK_SEL_SHIFT = 15,
221 NANDC_CLK_SEL_MASK = 0x1 << NANDC_CLK_SEL_SHIFT,
222 NANDC_CLK_SEL_NANDC = 0,
223 NANDC_CLK_SEL_NANDC_DIV50,
224 NANDC_DIV50_SHIFT = 8,
225 NANDC_DIV50_MASK = 0x1f << NANDC_DIV50_SHIFT,
226 NANDC_PLL_SHIFT = 6,
227 NANDC_PLL_MASK = 0x3 << NANDC_PLL_SHIFT,
228 NANDC_SEL_GPLL = 0,
229 NANDC_SEL_CPLL,
230 NANDC_SEL_NPLL,
231 NANDC_DIV_SHIFT = 0,
232 NANDC_DIV_MASK = 0x1f << NANDC_DIV_SHIFT,
233
234 /* CRU_CLKSEL20_CON */
235 EMMC_PLL_SHIFT = 14,
236 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
237 EMMC_SEL_GPLL = 0,
238 EMMC_SEL_CPLL,
239 EMMC_SEL_NPLL,
240 EMMC_SEL_24M,
241 EMMC_DIV_SHIFT = 0,
242 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT,
243
244 /* CRU_CLKSEL21_CON */
245 EMMC_CLK_SEL_SHIFT = 15,
246 EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT,
247 EMMC_CLK_SEL_EMMC = 0,
248 EMMC_CLK_SEL_EMMC_DIV50,
249 EMMC_DIV50_SHIFT = 0,
250 EMMC_DIV50_MASK = 0xff << EMMC_DIV_SHIFT,
251
252 /* CRU_CLKSEL22_CON */
253 GMAC_PLL_SEL_SHIFT = 14,
254 GMAC_PLL_SEL_MASK = 3 << GMAC_PLL_SEL_SHIFT,
255 GMAC_PLL_SEL_GPLL = 0,
256 GMAC_PLL_SEL_CPLL,
257 GMAC_PLL_SEL_NPLL,
258 CLK_GMAC_DIV_SHIFT = 8,
259 CLK_GMAC_DIV_MASK = 0x1f << CLK_GMAC_DIV_SHIFT,
260 SFC_PLL_SEL_SHIFT = 7,
261 SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT,
262 SFC_DIV_CON_SHIFT = 0,
263 SFC_DIV_CON_MASK = 0x7f,
264
265 /* CRU_CLK_SEL23_CON */
266 BUS_PLL_SEL_SHIFT = 15,
267 BUS_PLL_SEL_MASK = 1 << BUS_PLL_SEL_SHIFT,
268 BUS_PLL_SEL_GPLL = 0,
269 BUS_PLL_SEL_CPLL,
270 BUS_ACLK_DIV_SHIFT = 8,
271 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
272 RMII_CLK_SEL_SHIFT = 7,
273 RMII_CLK_SEL_MASK = 1 << RMII_CLK_SEL_SHIFT,
274 RMII_CLK_SEL_10M = 0,
275 RMII_CLK_SEL_100M,
276 RMII_EXTCLK_SEL_SHIFT = 6,
277 RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT,
278 RMII_EXTCLK_SEL_INT = 0,
279 RMII_EXTCLK_SEL_EXT,
280 PCLK_GMAC_DIV_SHIFT = 0,
281 PCLK_GMAC_DIV_MASK = 0x0f << PCLK_GMAC_DIV_SHIFT,
282
283 /* CRU_CLK_SEL24_CON */
284 BUS_PCLK_DIV_SHIFT = 8,
285 BUS_PCLK_DIV_MASK = 3 << BUS_PCLK_DIV_SHIFT,
286 BUS_HCLK_DIV_SHIFT = 0,
287 BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT,
288
289 /* CRU_CLK_SEL25_CON */
290 CRYPTO_APK_SEL_SHIFT = 14,
291 CRYPTO_APK_PLL_SEL_MASK = 3 << CRYPTO_APK_SEL_SHIFT,
292 CRYPTO_PLL_SEL_GPLL = 0,
293 CRYPTO_PLL_SEL_CPLL,
294 CRYPTO_PLL_SEL_NPLL = 0,
295 CRYPTO_APK_DIV_SHIFT = 8,
296 CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT,
297 CRYPTO_PLL_SEL_SHIFT = 6,
298 CRYPTO_PLL_SEL_MASK = 3 << CRYPTO_PLL_SEL_SHIFT,
299 CRYPTO_DIV_SHIFT = 0,
300 CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT,
301
302 /* CRU_CLK_SEL30_CON */
303 CLK_I2S1_DIV_CON_MASK = 0x7f,
304 CLK_I2S1_PLL_SEL_MASK = 0X1 << 8,
305 CLK_I2S1_PLL_SEL_GPLL = 0X0 << 8,
306 CLK_I2S1_PLL_SEL_NPLL = 0X1 << 8,
307 CLK_I2S1_SEL_MASK = 0x3 << 10,
308 CLK_I2S1_SEL_I2S1 = 0x0 << 10,
309 CLK_I2S1_SEL_FRAC = 0x1 << 10,
310 CLK_I2S1_SEL_MCLK_IN = 0x2 << 10,
311 CLK_I2S1_SEL_OSC = 0x3 << 10,
312 CLK_I2S1_OUT_SEL_MASK = 0x1 << 15,
313 CLK_I2S1_OUT_SEL_I2S1 = 0x0 << 15,
314 CLK_I2S1_OUT_SEL_OSC = 0x1 << 15,
315
316 /* CRU_CLK_SEL31_CON */
317 CLK_I2S1_FRAC_NUMERATOR_SHIFT = 16,
318 CLK_I2S1_FRAC_NUMERATOR_MASK = 0xffff << 16,
319 CLK_I2S1_FRAC_DENOMINATOR_SHIFT = 0,
320 CLK_I2S1_FRAC_DENOMINATOR_MASK = 0xffff,
321
322 /* CRU_CLK_SEL34_CON */
323 UART1_PLL_SEL_SHIFT = 14,
324 UART1_PLL_SEL_MASK = 3 << UART1_PLL_SEL_SHIFT,
325 UART1_PLL_SEL_GPLL = 0,
326 UART1_PLL_SEL_24M,
327 UART1_PLL_SEL_480M,
328 UART1_PLL_SEL_NPLL,
329 UART1_DIV_CON_SHIFT = 0,
330 UART1_DIV_CON_MASK = 0x1f << UART1_DIV_CON_SHIFT,
331
332 /* CRU_CLK_SEL35_CON */
333 UART1_CLK_SEL_SHIFT = 14,
334 UART1_CLK_SEL_MASK = 3 << UART1_PLL_SEL_SHIFT,
335 UART1_CLK_SEL_UART1 = 0,
336 UART1_CLK_SEL_UART1_NP5,
337 UART1_CLK_SEL_UART1_FRAC,
338 UART1_DIVNP5_SHIFT = 0,
339 UART1_DIVNP5_MASK = 0x1f << UART1_DIVNP5_SHIFT,
340
341 /* CRU_CLK_SEL37_CON */
342 UART2_PLL_SEL_SHIFT = 14,
343 UART2_PLL_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT,
344 UART2_PLL_SEL_GPLL = 0,
345 UART2_PLL_SEL_24M,
346 UART2_PLL_SEL_480M,
347 UART2_PLL_SEL_NPLL,
348 UART2_DIV_CON_SHIFT = 0,
349 UART2_DIV_CON_MASK = 0x1f << UART2_DIV_CON_SHIFT,
350
351 /* CRU_CLK_SEL38_CON */
352 UART2_CLK_SEL_SHIFT = 14,
353 UART2_CLK_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT,
354 UART2_CLK_SEL_UART2 = 0,
355 UART2_CLK_SEL_UART2_NP5,
356 UART2_CLK_SEL_UART2_FRAC,
357 UART2_DIVNP5_SHIFT = 0,
358 UART2_DIVNP5_MASK = 0x1f << UART2_DIVNP5_SHIFT,
359
Paul Kocialkowski4a7180d2019-11-28 15:27:52 +0100[diff] [blame]360 /* CRU_CLK_SEL40_CON */
361 UART3_PLL_SEL_SHIFT = 14,
362 UART3_PLL_SEL_MASK = 3 << UART3_PLL_SEL_SHIFT,
363 UART3_PLL_SEL_GPLL = 0,
364 UART3_PLL_SEL_24M,
365 UART3_PLL_SEL_480M,
366 UART3_PLL_SEL_NPLL,
367 UART3_DIV_CON_SHIFT = 0,
368 UART3_DIV_CON_MASK = 0x1f << UART3_DIV_CON_SHIFT,
369
370 /* CRU_CLK_SEL41_CON */
371 UART3_CLK_SEL_SHIFT = 14,
372 UART3_CLK_SEL_MASK = 3 << UART3_PLL_SEL_SHIFT,
373 UART3_CLK_SEL_UART3 = 0,
374 UART3_CLK_SEL_UART3_NP5,
375 UART3_CLK_SEL_UART3_FRAC,
376 UART3_DIVNP5_SHIFT = 0,
377 UART3_DIVNP5_MASK = 0x1f << UART3_DIVNP5_SHIFT,
378
Kever Yangba1033d2019-07-11 10:42:16 +0200[diff] [blame]379 /* CRU_CLK_SEL46_CON */
380 UART5_PLL_SEL_SHIFT = 14,
381 UART5_PLL_SEL_MASK = 3 << UART5_PLL_SEL_SHIFT,
382 UART5_PLL_SEL_GPLL = 0,
383 UART5_PLL_SEL_24M,
384 UART5_PLL_SEL_480M,
385 UART5_PLL_SEL_NPLL,
386 UART5_DIV_CON_SHIFT = 0,
387 UART5_DIV_CON_MASK = 0x1f << UART5_DIV_CON_SHIFT,
388
389 /* CRU_CLK_SEL47_CON */
390 UART5_CLK_SEL_SHIFT = 14,
391 UART5_CLK_SEL_MASK = 3 << UART5_PLL_SEL_SHIFT,
392 UART5_CLK_SEL_UART5 = 0,
393 UART5_CLK_SEL_UART5_NP5,
394 UART5_CLK_SEL_UART5_FRAC,
395 UART5_DIVNP5_SHIFT = 0,
396 UART5_DIVNP5_MASK = 0x1f << UART5_DIVNP5_SHIFT,
397
398 /* CRU_CLK_SEL49_CON */
399 CLK_I2C_PLL_SEL_GPLL = 0,
400 CLK_I2C_PLL_SEL_24M,
401 CLK_I2C_DIV_CON_MASK = 0x7f,
402 CLK_I2C_PLL_SEL_MASK = 1,
403 CLK_I2C1_PLL_SEL_SHIFT = 15,
404 CLK_I2C1_DIV_CON_SHIFT = 8,
405 CLK_I2C0_PLL_SEL_SHIFT = 7,
406 CLK_I2C0_DIV_CON_SHIFT = 0,
407
408 /* CRU_CLK_SEL50_CON */
409 CLK_I2C3_PLL_SEL_SHIFT = 15,
410 CLK_I2C3_DIV_CON_SHIFT = 8,
411 CLK_I2C2_PLL_SEL_SHIFT = 7,
412 CLK_I2C2_DIV_CON_SHIFT = 0,
413
414 /* CRU_CLK_SEL52_CON */
415 CLK_PWM_PLL_SEL_GPLL = 0,
416 CLK_PWM_PLL_SEL_24M,
417 CLK_PWM_DIV_CON_MASK = 0x7f,
418 CLK_PWM_PLL_SEL_MASK = 1,
419 CLK_PWM1_PLL_SEL_SHIFT = 15,
420 CLK_PWM1_DIV_CON_SHIFT = 8,
421 CLK_PWM0_PLL_SEL_SHIFT = 7,
422 CLK_PWM0_DIV_CON_SHIFT = 0,
423
424 /* CRU_CLK_SEL53_CON */
425 CLK_SPI_PLL_SEL_GPLL = 0,
426 CLK_SPI_PLL_SEL_24M,
427 CLK_SPI_DIV_CON_MASK = 0x7f,
428 CLK_SPI_PLL_SEL_MASK = 1,
429 CLK_SPI1_PLL_SEL_SHIFT = 15,
430 CLK_SPI1_DIV_CON_SHIFT = 8,
431 CLK_SPI0_PLL_SEL_SHIFT = 7,
432 CLK_SPI0_DIV_CON_SHIFT = 0,
433
434 /* CRU_CLK_SEL55_CON */
435 CLK_SARADC_DIV_CON_SHIFT = 0,
436 CLK_SARADC_DIV_CON_MASK = 0x7ff,
437
438 /* CRU_CLK_GATE10_CON */
439 CLK_I2S1_OUT_MCLK_PAD_MASK = 0x1 << 9,
440 CLK_I2S1_OUT_MCLK_PAD_ENABLE = 0x1 << 9,
441 CLK_I2S1_OUT_MCLK_PAD_DISABLE = 0x0 << 9,
442
443 /* CRU_PMU_MODE */
444 GPLL_MODE_SHIFT = 0,
445 GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT,
446
447 /* CRU_PMU_CLK_SEL0_CON */
448 CLK_PMU_PCLK_DIV_SHIFT = 0,
449 CLK_PMU_PCLK_DIV_MASK = 0x1f << CLK_PMU_PCLK_DIV_SHIFT,
450};
451#endif