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Sergei Poselenovf2bf96c2008-04-30 11:42:50 +02001/*
2 * (C) Copyright 2008
3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
4 *
5 * Wolfgang Denk <wd@denx.de>
6 * Copyright 2004 Freescale Semiconductor.
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
9 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +020010 * SPDX-License-Identifier: GPL-2.0+
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020011 */
12
13/*
14 * Socrates
15 */
16
17#ifndef __CONFIG_H
18#define __CONFIG_H
19
20/* High Level Configuration Options */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020021#define CONFIG_SOCRATES 1
22
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020023#define CONFIG_SYS_TEXT_BASE 0xfff80000
24
Gabor Juhosb4458732013-05-30 07:06:12 +000025#define CONFIG_PCI_INDIRECT_BRIDGE
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020026
27#define CONFIG_TSEC_ENET /* tsec ethernet support */
28
29#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
Detlev Zundel0244f672008-08-15 15:42:12 +020030#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020031
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020032/*
33 * Only possible on E500 Version 2 or newer cores.
34 */
35#define CONFIG_ENABLE_36BIT_PHYS 1
36
37/*
38 * sysclk for MPC85xx
39 *
40 * Two valid values are:
41 * 33000000
42 * 66000000
43 *
44 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
45 * is likely the desired value here, so that is now the default.
46 * The board, however, can run at 66MHz. In any event, this value
47 * must match the settings of some switches. Details can be found
48 * in the README.mpc85xxads.
49 */
50
51#ifndef CONFIG_SYS_CLK_FREQ
52#define CONFIG_SYS_CLK_FREQ 66666666
53#endif
54
55/*
56 * These can be toggled for performance analysis, otherwise use default.
57 */
58#define CONFIG_L2_CACHE /* toggle L2 cache */
59#define CONFIG_BTB /* toggle branch predition */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020060
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020061#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020062
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020063#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
64#define CONFIG_SYS_MEMTEST_START 0x00400000
65#define CONFIG_SYS_MEMTEST_END 0x00C00000
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020066
Timur Tabid8f341c2011-08-04 18:03:41 -050067#define CONFIG_SYS_CCSRBAR 0xE0000000
68#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020069
Kumar Gala01135a82008-08-26 22:56:56 -050070/* DDR Setup */
Kumar Gala01135a82008-08-26 22:56:56 -050071#undef CONFIG_FSL_DDR_INTERACTIVE
72#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
73#define CONFIG_DDR_SPD
74
75#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
76#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
77
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020078#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
79#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala01135a82008-08-26 22:56:56 -050080#define CONFIG_VERY_BIG_RAM
81
Kumar Gala01135a82008-08-26 22:56:56 -050082#define CONFIG_DIMM_SLOTS_PER_CTLR 1
83#define CONFIG_CHIP_SELECTS_PER_CTRL 2
84
85/* I2C addresses of SPD EEPROMs */
Anatolij Gustschin2c04bc32008-09-17 11:45:51 +020086#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020087
88#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
89
90/* Hardcoded values, to use instead of SPD */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020091#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
92#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
93#define CONFIG_SYS_DDR_TIMING_0 0x00260802
94#define CONFIG_SYS_DDR_TIMING_1 0x3935D322
95#define CONFIG_SYS_DDR_TIMING_2 0x14904CC8
96#define CONFIG_SYS_DDR_MODE 0x00480432
97#define CONFIG_SYS_DDR_INTERVAL 0x030C0100
98#define CONFIG_SYS_DDR_CONFIG_2 0x04400000
99#define CONFIG_SYS_DDR_CONFIG 0xC3008000
100#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000
101#define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200102
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200103/*
104 * Flash on the LocalBus
105 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200106#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200107
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200108#define CONFIG_SYS_FLASH0 0xFE000000
109#define CONFIG_SYS_FLASH1 0xFC000000
110#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200111
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200112#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
113#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200114
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200115#define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */
116#define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */
117#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */
118#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200119
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200120#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200121#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200122
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200123#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
124#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
125#undef CONFIG_SYS_FLASH_CHECKSUM
126#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
127#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200128
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200129#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200130
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200131#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
132#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
133#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
134#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200135
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200136#define CONFIG_SYS_INIT_RAM_LOCK 1
137#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200138#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200139
Wolfgang Denk0191e472010-10-26 14:34:52 +0200140#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200141#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200142
Detlev Zundel2aba8a12010-04-14 11:32:20 +0200143#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200144#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */
Detlev Zundel0244f672008-08-15 15:42:12 +0200145
146/* FPGA and NAND */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200147#define CONFIG_SYS_FPGA_BASE 0xc0000000
148#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
149#define CONFIG_SYS_HMI_BASE 0xc0010000
150#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
151#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */
Detlev Zundel0244f672008-08-15 15:42:12 +0200152
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200153#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
154#define CONFIG_SYS_MAX_NAND_DEVICE 1
Detlev Zundel0244f672008-08-15 15:42:12 +0200155#define CONFIG_CMD_NAND
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200156
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200157/* LIME GDC */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200158#define CONFIG_SYS_LIME_BASE 0xc8000000
159#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
160#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */
161#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200162
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200163#define CONFIG_VIDEO_MB862xx
Anatolij Gustschine7e44a02009-10-23 12:03:14 +0200164#define CONFIG_VIDEO_MB862xx_ACCEL
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200165#define CONFIG_VIDEO_LOGO
166#define CONFIG_VIDEO_BMP_LOGO
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200167#define VIDEO_FB_16BPP_PIXEL_SWAP
Wolfgang Grandeggere1b05842009-10-23 12:03:15 +0200168#define VIDEO_FB_16BPP_WORD_SWAP
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200169#define CONFIG_SPLASH_SCREEN
170#define CONFIG_VIDEO_BMP_GZIP
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200171#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200172
Wolfgang Grandeggerb890f9e2009-10-23 12:03:13 +0200173/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
174#define CONFIG_SYS_MB862xx_CCF 0x10000
175/* SDRAM parameter */
176#define CONFIG_SYS_MB862xx_MMR 0x4157BA63
177
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200178/* Serial Port */
179
180#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200181#define CONFIG_SYS_NS16550_SERIAL
182#define CONFIG_SYS_NS16550_REG_SIZE 1
183#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200184
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200185#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
186#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200187
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200188#define CONFIG_SYS_BAUDRATE_TABLE \
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200189 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
190
191#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillipsf7758c12010-07-14 19:47:18 -0500192#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200193
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200194/*
195 * I2C
196 */
Heiko Schocherf2850742012-10-24 13:48:22 +0200197#define CONFIG_SYS_I2C
198#define CONFIG_SYS_I2C_FSL
199#define CONFIG_SYS_FSL_I2C_SPEED 102124
200#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
201#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
202#define CONFIG_SYS_FSL_I2C2_SPEED 102124
203#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
204#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Detlev Zundel0244f672008-08-15 15:42:12 +0200205
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200206/* I2C RTC */
Sergei Poselenov09842c52008-05-07 15:10:49 +0200207#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200208#define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200209
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200210/* I2C W83782G HW-Monitoring IC */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200211#define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200212
Sergei Poselenov92cdc442008-05-27 10:36:07 +0200213/* I2C temp sensor */
214/* Socrates uses Maxim's DS75, which is compatible with LM75 */
215#define CONFIG_DTT_LM75 1
216#define CONFIG_DTT_SENSORS {4} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200217#define CONFIG_SYS_DTT_MAX_TEMP 125
218#define CONFIG_SYS_DTT_LOW_TEMP -55
219#define CONFIG_SYS_DTT_HYSTERESIS 3
220#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
Sergei Poselenov92cdc442008-05-27 10:36:07 +0200221
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200222/*
223 * General PCI
224 * Memory space is mapped 1-1.
225 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200226#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200227
Sergei Poselenove13be1a2008-05-27 13:47:00 +0200228/* PCI is clocked by the external source at 33 MHz */
229#define CONFIG_PCI_CLK_FREQ 33000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200230#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
231#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
232#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
233#define CONFIG_SYS_PCI1_IO_BASE 0xE2000000
234#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
235#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200236
237#if defined(CONFIG_PCI)
Sergei Poselenov18343da2008-06-06 15:42:39 +0200238#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200239#endif /* CONFIG_PCI */
240
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200241#define CONFIG_MII 1 /* MII PHY management */
242#define CONFIG_TSEC1 1
243#define CONFIG_TSEC1_NAME "TSEC0"
Sergei Poselenov6be57752008-05-08 17:46:23 +0200244#define CONFIG_TSEC3 1
245#define CONFIG_TSEC3_NAME "TSEC1"
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200246#undef CONFIG_MPC85XX_FEC
247
248#define TSEC1_PHY_ADDR 0
Sergei Poselenov6be57752008-05-08 17:46:23 +0200249#define TSEC3_PHY_ADDR 1
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200250
251#define TSEC1_PHYIDX 0
Sergei Poselenov6be57752008-05-08 17:46:23 +0200252#define TSEC3_PHYIDX 0
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200253#define TSEC1_FLAGS TSEC_GIGABIT
Sergei Poselenov6be57752008-05-08 17:46:23 +0200254#define TSEC3_FLAGS TSEC_GIGABIT
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200255
Sergei Poselenov6be57752008-05-08 17:46:23 +0200256/* Options are: TSEC[0,1] */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200257#define CONFIG_ETHPRIME "TSEC0"
258#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
259
Sergei Poselenov09842c52008-05-07 15:10:49 +0200260#define CONFIG_HAS_ETH0
261#define CONFIG_HAS_ETH1
262
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200263/*
264 * Environment
265 */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200266#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200267#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200268#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200269#define CONFIG_ENV_SIZE 0x4000
270#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
271#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200272
273#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200274#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200275
276#define CONFIG_TIMESTAMP /* Print image info with ts */
277
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200278/*
279 * BOOTP options
280 */
281#define CONFIG_BOOTP_BOOTFILESIZE
282#define CONFIG_BOOTP_BOOTPATH
283#define CONFIG_BOOTP_GATEWAY
284#define CONFIG_BOOTP_HOSTNAME
285
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200286/*
287 * Command line configuration.
288 */
Sergei Poselenov92cdc442008-05-27 10:36:07 +0200289#define CONFIG_CMD_DTT
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200290#undef CONFIG_CMD_EEPROM
Detlev Zundel0244f672008-08-15 15:42:12 +0200291#define CONFIG_CMD_SDRAM
Becky Bruceee888da2010-06-17 11:37:25 -0500292#define CONFIG_CMD_REGINFO
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200293
294#if defined(CONFIG_PCI)
295 #define CONFIG_CMD_PCI
296#endif
297
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200298#undef CONFIG_WATCHDOG /* watchdog disabled */
299
300/*
301 * Miscellaneous configurable options
302 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200303#define CONFIG_SYS_LONGHELP /* undef to save memory */
304#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200305
306#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200307 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200308#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200309 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200310#endif
311
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200312#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size */
313#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
314#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200315
316/*
317 * For booting Linux, the board info and command line data
318 * have to be in the first 8 MB of memory, since this is
319 * the maximum mapped by the Linux kernel during initialization.
320 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200321#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200322
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200323#if defined(CONFIG_CMD_KGDB)
324#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200325#endif
326
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200327#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
328
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200329
330#define CONFIG_PREBOOT "echo;" \
Detlev Zundel0244f672008-08-15 15:42:12 +0200331 "echo Welcome on the ABB Socrates Board;" \
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200332 "echo"
333
334#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
335
336#define CONFIG_EXTRA_ENV_SETTINGS \
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200337 "netdev=eth0\0" \
338 "consdev=ttyS0\0" \
Detlev Zundel0244f672008-08-15 15:42:12 +0200339 "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \
340 "bootfile=/home/tftp/syscon3/uImage\0" \
341 "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \
342 "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \
343 "uboot_addr=FFFA0000\0" \
344 "kernel_addr=FE000000\0" \
345 "fdt_addr=FE1E0000\0" \
346 "ramdisk_addr=FE200000\0" \
347 "fdt_addr_r=B00000\0" \
348 "kernel_addr_r=200000\0" \
349 "ramdisk_addr_r=400000\0" \
350 "rootpath=/opt/eldk/ppc_85xxDP\0" \
351 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200352 "nfsargs=setenv bootargs root=/dev/nfs rw " \
353 "nfsroot=$serverip:$rootpath\0" \
Detlev Zundel0244f672008-08-15 15:42:12 +0200354 "addcons=setenv bootargs $bootargs " \
355 "console=$consdev,$baudrate\0" \
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200356 "addip=setenv bootargs $bootargs " \
357 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
358 ":$hostname:$netdev:off panic=1\0" \
Detlev Zundel0244f672008-08-15 15:42:12 +0200359 "boot_nor=run ramargs addcons;" \
Sergei Poselenov09842c52008-05-07 15:10:49 +0200360 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
Sergei Poselenov09842c52008-05-07 15:10:49 +0200361 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
362 "tftp ${fdt_addr_r} ${fdt_file}; " \
363 "run nfsargs addip addcons;" \
364 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
Detlev Zundel0244f672008-08-15 15:42:12 +0200365 "update_uboot=tftp 100000 ${uboot_file};" \
366 "protect off fffa0000 ffffffff;" \
367 "era fffa0000 ffffffff;" \
368 "cp.b 100000 fffa0000 ${filesize};" \
369 "setenv filesize;saveenv\0" \
370 "update_kernel=tftp 100000 ${bootfile};" \
371 "era fe000000 fe1dffff;" \
372 "cp.b 100000 fe000000 ${filesize};" \
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200373 "setenv filesize;saveenv\0" \
Detlev Zundel0244f672008-08-15 15:42:12 +0200374 "update_fdt=tftp 100000 ${fdt_file};" \
375 "era fe1e0000 fe1fffff;" \
376 "cp.b 100000 fe1e0000 ${filesize};" \
377 "setenv filesize;saveenv\0" \
378 "update_initrd=tftp 100000 ${initrd_file};" \
379 "era fe200000 fe9fffff;" \
380 "cp.b 100000 fe200000 ${filesize};" \
381 "setenv filesize;saveenv\0" \
382 "clean_data=era fea00000 fff5ffff\0" \
383 "usbargs=setenv bootargs root=/dev/sda1 rw\0" \
384 "load_usb=usb start;" \
385 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \
386 "boot_usb=run load_usb usbargs addcons;" \
387 "bootm ${kernel_addr_r} - ${fdt_addr};" \
388 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200389 ""
Detlev Zundel0244f672008-08-15 15:42:12 +0200390#define CONFIG_BOOTCOMMAND "run boot_nor"
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200391
Sergei Poselenov09842c52008-05-07 15:10:49 +0200392/* pass open firmware flat tree */
Sergei Poselenov09842c52008-05-07 15:10:49 +0200393
Sergei Poselenoveeaaa612008-05-27 11:49:13 +0200394/* USB support */
395#define CONFIG_USB_OHCI_NEW 1
396#define CONFIG_PCI_OHCI 1
397#define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */
Yuri Tikhonov11af42c2008-09-04 11:19:05 +0200398#define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200399#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
400#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
401#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
Sergei Poselenoveeaaa612008-05-27 11:49:13 +0200402
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200403#endif /* __CONFIG_H */