blob: 8eb4f8fc950bb080aeb90106ebc1b4d70f445d15 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +02002/*
3 * (C) Copyright 2008
4 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +02005 */
6
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +02007#include <common.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -07008#include <init.h>
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +02009#include <asm/processor.h>
10#include <asm/immap_85xx.h>
York Sunf0626592013-09-30 09:22:09 -070011#include <fsl_ddr_sdram.h>
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020012#include <asm/processor.h>
13#include <asm/mmu.h>
14#include <spd_sdram.h>
15
16
17#if !defined(CONFIG_SPD_EEPROM)
18/*
19 * Autodetect onboard DDR SDRAM on 85xx platforms
20 *
21 * NOTE: Some of the hardcoded values are hardware dependant,
22 * so this should be extended for other future boards
23 * using this routine!
24 */
Becky Bruce5e35d8a2010-12-17 17:17:56 -060025phys_size_t fixed_sdram(void)
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020026{
York Suna21803d2013-11-18 10:29:32 -080027 struct ccsr_ddr __iomem *ddr =
28 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020029
30 /*
31 * Disable memory controller.
32 */
33 ddr->cs0_config = 0;
34 ddr->sdram_cfg = 0;
35
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020036 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
37 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
38 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
39 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
40 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
41 ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
42 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
43 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2;
44 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL;
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020045
46 asm ("sync;isync;msync");
47 udelay(1000);
48
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020049 ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG;
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020050 asm ("sync; isync; msync");
51 udelay(1000);
52
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020053 if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) {
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020054 /*
55 * OK, size detected -> all done
56 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020057 return CONFIG_SYS_SDRAM_SIZE<<20;
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020058 }
59
60 return 0; /* nothing found ! */
61}
62#endif
63
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020064#if defined(CONFIG_SYS_DRAM_TEST)
Simon Glass0ffd9db2019-12-28 10:45:06 -070065int testdram(void)
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020066{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020067 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
68 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020069 uint *p;
70
71 printf ("SDRAM test phase 1:\n");
72 for (p = pstart; p < pend; p++)
73 *p = 0xaaaaaaaa;
74
75 for (p = pstart; p < pend; p++) {
76 if (*p != 0xaaaaaaaa) {
77 printf ("SDRAM test fails at: %08x\n", (uint) p);
78 return 1;
79 }
80 }
81
82 printf ("SDRAM test phase 2:\n");
83 for (p = pstart; p < pend; p++)
84 *p = 0x55555555;
85
86 for (p = pstart; p < pend; p++) {
87 if (*p != 0x55555555) {
88 printf ("SDRAM test fails at: %08x\n", (uint) p);
89 return 1;
90 }
91 }
92
93 printf ("SDRAM test passed.\n");
94 return 0;
95}
96#endif