blob: 78aaa9e13a3a88847bb6b82092a2f79931b1eb92 [file] [log] [blame]
Guennadi Liakhovetskib2d42742008-08-31 00:39:47 +02001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8 *
9 * (C) Copyright 2008
10 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#include <common.h>
Ben Warren3bf5d832009-08-25 13:09:37 -070032#include <netdev.h>
Minkyu Kang960a8e12009-11-04 16:07:59 +090033#include <asm/arch/s3c6400.h>
Guennadi Liakhovetskib2d42742008-08-31 00:39:47 +020034
35/* ------------------------------------------------------------------------- */
36#define CS8900_Tacs 0x0 /* 0clk address set-up */
37#define CS8900_Tcos 0x4 /* 4clk chip selection set-up */
38#define CS8900_Tacc 0xE /* 14clk access cycle */
39#define CS8900_Tcoh 0x1 /* 1clk chip selection hold */
40#define CS8900_Tah 0x4 /* 4clk address holding time */
41#define CS8900_Tacp 0x6 /* 6clk page mode access cycle */
42#define CS8900_PMC 0x0 /* normal(1data)page mode configuration */
43
44static inline void delay(unsigned long loops)
45{
46 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
47 "bne 1b"
48 : "=r" (loops) : "0" (loops));
49}
50
51/*
52 * Miscellaneous platform dependent initialisations
53 */
54
55static void cs8900_pre_init(void)
56{
57 SROM_BW_REG &= ~(0xf << 4);
58 SROM_BW_REG |= (1 << 7) | (1 << 6) | (1 << 4);
59 SROM_BC1_REG = ((CS8900_Tacs << 28) + (CS8900_Tcos << 24) +
60 (CS8900_Tacc << 16) + (CS8900_Tcoh << 12) +
61 (CS8900_Tah << 8) + (CS8900_Tacp << 4) + CS8900_PMC);
62}
63
64int board_init(void)
65{
66 DECLARE_GLOBAL_DATA_PTR;
67
68 cs8900_pre_init();
69
70 /* NOR-flash in SROM0 */
71
72 /* Enable WAIT */
73 SROM_BW_REG |= 4 | 8 | 1;
74
75 gd->bd->bi_arch_number = MACH_TYPE;
76 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
77
78 return 0;
79}
80
81int dram_init(void)
82{
83 DECLARE_GLOBAL_DATA_PTR;
84
85 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
86 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
87
88 return 0;
89}
90
91#ifdef CONFIG_DISPLAY_BOARDINFO
92int checkboard(void)
93{
94 printf("Board: SMDK6400\n");
95 return 0;
96}
97#endif
98
99#ifdef CONFIG_ENABLE_MMU
100ulong virt_to_phy_smdk6400(ulong addr)
101{
102 if ((0xc0000000 <= addr) && (addr < 0xc8000000))
103 return addr - 0xc0000000 + 0x50000000;
104 else
105 printf("do not support this address : %08lx\n", addr);
106
107 return addr;
108}
109#endif
110
Guennadi Liakhovetskib2d42742008-08-31 00:39:47 +0200111ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info)
112{
113 if (banknum == 0) { /* non-CFI boot flash */
114 info->portwidth = FLASH_CFI_16BIT;
115 info->chipwidth = FLASH_CFI_BY16;
116 info->interface = FLASH_CFI_X16;
117 return 1;
118 } else
119 return 0;
120}
Ben Warren3bf5d832009-08-25 13:09:37 -0700121
122#ifdef CONFIG_CMD_NET
123int board_eth_init(bd_t *bis)
124{
125 int rc = 0;
126#ifdef CONFIG_CS8900
127 rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
128#endif
129 return rc;
130}
131#endif