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Siarhei Siamashka3848f972016-03-29 17:29:11 +02001/*
2 * Copyright (c) 2016 ARM Ltd.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/dts-v1/;
44
Andre Przywara8d65e613e2017-05-24 10:34:56 +010045#include "sun50i-a64.dtsi"
46
47#include <dt-bindings/gpio/gpio.h>
Siarhei Siamashka3848f972016-03-29 17:29:11 +020048
49/ {
50 model = "Pine64";
Andre Przywara36748112016-05-04 22:15:33 +010051 compatible = "pine64,pine64", "allwinner,sun50i-a64";
Siarhei Siamashka3848f972016-03-29 17:29:11 +020052
Andre Przywara8d65e613e2017-05-24 10:34:56 +010053 aliases {
Andre Przywara0fcb8302018-07-04 14:16:35 +010054 ethernet0 = &emac;
Andre Przywara8d65e613e2017-05-24 10:34:56 +010055 serial0 = &uart0;
Andre Przywara0fcb8302018-07-04 14:16:35 +010056 serial1 = &uart1;
57 serial2 = &uart2;
58 serial3 = &uart3;
59 serial4 = &uart4;
Andre Przywara8d65e613e2017-05-24 10:34:56 +010060 };
61
Siarhei Siamashka3848f972016-03-29 17:29:11 +020062 chosen {
63 stdout-path = "serial0:115200n8";
64 };
Andre Przywara0fcb8302018-07-04 14:16:35 +010065};
Siarhei Siamashka3848f972016-03-29 17:29:11 +020066
Andre Przywara0fcb8302018-07-04 14:16:35 +010067&ehci0 {
68 status = "okay";
Siarhei Siamashka3848f972016-03-29 17:29:11 +020069};
Andre Przywara8d65e613e2017-05-24 10:34:56 +010070
71&ehci1 {
72 status = "okay";
Andre Przywara0fcb8302018-07-04 14:16:35 +010073};
74
75&emac {
76 pinctrl-names = "default";
77 pinctrl-0 = <&rmii_pins>;
78 phy-mode = "rmii";
79 phy-handle = <&ext_rmii_phy1>;
80 phy-supply = <&reg_dc1sw>;
81 status = "okay";
82
Andre Przywara8d65e613e2017-05-24 10:34:56 +010083};
84
85&i2c1 {
86 pinctrl-names = "default";
87 pinctrl-0 = <&i2c1_pins>;
88 status = "okay";
89};
90
91&i2c1_pins {
92 bias-pull-up;
93};
94
Andre Przywara0fcb8302018-07-04 14:16:35 +010095&mdio {
96 ext_rmii_phy1: ethernet-phy@1 {
97 compatible = "ethernet-phy-ieee802.3-c22";
98 reg = <1>;
99 };
100};
101
Andre Przywara8d65e613e2017-05-24 10:34:56 +0100102&mmc0 {
103 pinctrl-names = "default";
104 pinctrl-0 = <&mmc0_pins>;
Andre Przywara0fcb8302018-07-04 14:16:35 +0100105 vmmc-supply = <&reg_dcdc1>;
106 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
Andre Przywara8d65e613e2017-05-24 10:34:56 +0100107 disable-wp;
108 bus-width = <4>;
109 status = "okay";
110};
111
Andre Przywara0fcb8302018-07-04 14:16:35 +0100112&ohci0 {
113 status = "okay";
114};
115
Andre Przywara8d65e613e2017-05-24 10:34:56 +0100116&ohci1 {
117 status = "okay";
Andre Przywara0fcb8302018-07-04 14:16:35 +0100118};
119
120&r_rsb {
121 status = "okay";
122
123 axp803: pmic@3a3 {
124 compatible = "x-powers,axp803";
125 reg = <0x3a3>;
126 interrupt-parent = <&r_intc>;
127 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
128 };
129};
130
131#include "axp803.dtsi"
132
133&reg_aldo2 {
134 regulator-always-on;
135 regulator-min-microvolt = <1800000>;
136 regulator-max-microvolt = <3300000>;
137 regulator-name = "vcc-pl";
138};
139
140&reg_aldo3 {
141 regulator-always-on;
142 regulator-min-microvolt = <3000000>;
143 regulator-max-microvolt = <3000000>;
144 regulator-name = "vcc-pll-avcc";
Andre Przywara8d65e613e2017-05-24 10:34:56 +0100145};
146
Andre Przywara0fcb8302018-07-04 14:16:35 +0100147&reg_dc1sw {
148 regulator-name = "vcc-phy";
149};
150
151&reg_dcdc1 {
152 regulator-always-on;
153 regulator-min-microvolt = <3300000>;
154 regulator-max-microvolt = <3300000>;
155 regulator-name = "vcc-3v3";
156};
157
158&reg_dcdc2 {
159 regulator-always-on;
160 regulator-min-microvolt = <1040000>;
161 regulator-max-microvolt = <1300000>;
162 regulator-name = "vdd-cpux";
163};
164
165/* DCDC3 is polyphased with DCDC2 */
166
167/*
168 * The DRAM chips used by Pine64 boards are DDR3L-compatible, so they can
169 * work at 1.35V with less power consumption.
170 * As AXP803 DCDC5 cannot reach 1.35V accurately, use 1.36V instead.
171 */
172&reg_dcdc5 {
173 regulator-always-on;
174 regulator-min-microvolt = <1360000>;
175 regulator-max-microvolt = <1360000>;
176 regulator-name = "vcc-dram";
177};
178
179&reg_dcdc6 {
180 regulator-always-on;
181 regulator-min-microvolt = <1100000>;
182 regulator-max-microvolt = <1100000>;
183 regulator-name = "vdd-sys";
184};
185
186&reg_dldo1 {
187 regulator-min-microvolt = <3300000>;
188 regulator-max-microvolt = <3300000>;
189 regulator-name = "vcc-hdmi";
190};
191
192&reg_dldo2 {
193 regulator-min-microvolt = <3300000>;
194 regulator-max-microvolt = <3300000>;
195 regulator-name = "vcc-mipi";
196};
197
198&reg_dldo4 {
199 regulator-min-microvolt = <3300000>;
200 regulator-max-microvolt = <3300000>;
201 regulator-name = "vcc-wifi";
202};
203
204&reg_eldo1 {
205 regulator-min-microvolt = <1800000>;
206 regulator-max-microvolt = <1800000>;
207 regulator-name = "cpvdd";
208};
209
210&reg_fldo1 {
211 regulator-min-microvolt = <1200000>;
212 regulator-max-microvolt = <1200000>;
213 regulator-name = "vcc-1v2-hsic";
214};
215
216/*
217 * The A64 chip cannot work without this regulator off, although
218 * it seems to be only driving the AR100 core.
219 * Maybe we don't still know well about CPUs domain.
220 */
221&reg_fldo2 {
222 regulator-always-on;
223 regulator-min-microvolt = <1100000>;
224 regulator-max-microvolt = <1100000>;
225 regulator-name = "vdd-cpus";
226};
227
228&reg_rtc_ldo {
229 regulator-name = "vcc-rtc";
230};
231
232/* On Euler connector */
233&spdif {
234 status = "disabled";
235};
236
237/* On Exp and Euler connectors */
Andre Przywara8d65e613e2017-05-24 10:34:56 +0100238&uart0 {
239 pinctrl-names = "default";
240 pinctrl-0 = <&uart0_pins_a>;
241 status = "okay";
242};
243
Andre Przywara0fcb8302018-07-04 14:16:35 +0100244/* On Wifi/BT connector, with RTS/CTS */
245&uart1 {
246 pinctrl-names = "default";
247 pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
248 status = "disabled";
249};
250
251/* On Pi-2 connector */
252&uart2 {
253 pinctrl-names = "default";
254 pinctrl-0 = <&uart2_pins>;
255 status = "disabled";
256};
257
258/* On Euler connector */
259&uart3 {
260 pinctrl-names = "default";
261 pinctrl-0 = <&uart3_pins>;
262 status = "disabled";
263};
264
265/* On Euler connector, RTS/CTS optional */
266&uart4 {
267 pinctrl-names = "default";
268 pinctrl-0 = <&uart4_pins>;
269 status = "disabled";
270};
271
Andre Przywara8d65e613e2017-05-24 10:34:56 +0100272&usb_otg {
273 dr_mode = "host";
274 status = "okay";
275};
276
277&usbphy {
278 status = "okay";
279};