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git01.mediatek.com / filogic / uboot / 89f00f292a464448757b5e330546b8fd215093c8 / . / arch / arm / dts / k3-am65.dtsi
blob: a3abd146d104f929a01b5b10bfab94537b8083db [file] [log] [blame]
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM6 SoC Family
4 *
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
Andreas Dannenbergd20cf7b2019-06-04 18:08:15 -0500[diff] [blame]11#include <dt-bindings/pinctrl/k3.h>
Lokesh Vutla61ff6a32019-06-07 19:24:47 +0530[diff] [blame]12#include <dt-bindings/soc/ti,sci_pm_domain.h>
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]13
14/ {
15 model = "Texas Instruments K3 AM654 SoC";
16 compatible = "ti,am654";
17 interrupt-parent = <&gic500>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]21 aliases {
22 serial0 = &wkup_uart0;
23 serial1 = &mcu_uart0;
24 serial2 = &main_uart0;
25 serial3 = &main_uart1;
26 serial4 = &main_uart2;
Andreas Dannenberge3179be2019-06-04 18:08:14 -0500[diff] [blame]27 i2c0 = &wkup_i2c0;
28 i2c1 = &mcu_i2c0;
29 i2c2 = &main_i2c0;
30 i2c3 = &main_i2c1;
31 i2c4 = &main_i2c2;
32 i2c5 = &main_i2c3;
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]33 };
34
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]35 chosen { };
36
37 firmware {
38 optee {
39 compatible = "linaro,optee-tz";
40 method = "smc";
41 };
42
43 psci: psci {
44 compatible = "arm,psci-1.0";
45 method = "smc";
46 };
47 };
48
49 a53_timer0: timer-cl0-cpu0 {
50 compatible = "arm,armv8-timer";
51 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
52 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
53 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
54 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
55 };
56
57 pmu: pmu {
58 compatible = "arm,armv8-pmuv3";
59 /* Recommendation from GIC500 TRM Table A.3 */
60 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
61 };
62
63 cbass_main: interconnect@100000 {
64 compatible = "simple-bus";
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]65 #address-cells = <2>;
66 #size-cells = <2>;
67 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
68 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
69 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
70 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
71 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]72 /* MCUSS Range */
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]73 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
74 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
Grygorii Strashkob33dd702019-07-09 10:30:35 +0530[diff] [blame]75 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]76 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
77 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
78 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
79 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>;
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]80
81 cbass_mcu: interconnect@28380000 {
82 compatible = "simple-bus";
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]83 #address-cells = <2>;
84 #size-cells = <2>;
85 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
86 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
Grygorii Strashkob33dd702019-07-09 10:30:35 +0530[diff] [blame]87 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]88 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
89 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
90 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
91 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; /* OSPI space 1 */
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]92
93 cbass_wakeup: interconnect@42040000 {
94 compatible = "simple-bus";
95 #address-cells = <1>;
96 #size-cells = <1>;
97 /* WKUP Basic peripherals */
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]98 ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]99 };
100 };
101 };
102};
103
104/* Now include the peripherals for each bus segments */
105#include "k3-am65-main.dtsi"
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]106#include "k3-am65-mcu.dtsi"
107#include "k3-am65-wakeup.dtsi"