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Stephen Warren185ad872016-06-17 09:43:58 -06001menu "Reset Controller Support"
2
3config DM_RESET
4 bool "Enable reset controllers using Driver Model"
5 depends on DM && OF_CONTROL
6 help
7 Enable support for the reset controller driver class. Many hardware
8 modules are equipped with a reset signal, typically driven by some
9 reset controller hardware module within the chip. In U-Boot, reset
10 controller drivers allow control over these reset signals. In some
11 cases this API is applicable to chips outside the CPU as well,
12 although driving such reset isgnals using GPIOs may be more
13 appropriate in this case.
14
Stephen Warren6488e642016-06-17 09:43:59 -060015config SANDBOX_RESET
16 bool "Enable the sandbox reset test driver"
17 depends on DM_MAILBOX && SANDBOX
18 help
19 Enable support for a test reset controller implementation, which
20 simply accepts requests to reset various HW modules without actually
21 doing anything beyond a little error checking.
22
Patrice Chotard1235aa02017-03-22 10:54:03 +010023config STI_RESET
24 bool "Enable the STi reset"
25 depends on ARCH_STI
26 help
27 Support for reset controllers on STMicroelectronics STiH407 family SoCs.
28 Say Y if you want to control reset signals provided by system config
29 block.
30
Patrice Chotard5c121e12017-09-13 18:00:07 +020031config STM32_RESET
32 bool "Enable the STM32 reset"
Trevor Woerner2bcc1ed2020-05-06 08:02:42 -040033 depends on ARCH_STM32 || ARCH_STM32MP
Patrice Chotard5c121e12017-09-13 18:00:07 +020034 help
35 Support for reset controllers on STMicroelectronics STM32 family SoCs.
Trevor Woernere3d9c992020-05-06 08:02:43 -040036 This reset driver is compatible with STM32 F4/F7 and H7 SoCs.
Patrice Chotard5c121e12017-09-13 18:00:07 +020037
Stephen Warren3017ab52016-09-13 10:45:58 -060038config TEGRA_CAR_RESET
39 bool "Enable Tegra CAR-based reset driver"
40 depends on TEGRA_CAR
41 help
42 Enable support for manipulating Tegra's on-SoC reset signals via
43 direct register access to the Tegra CAR (Clock And Reset controller).
44
Stephen Warrenfccc9c52016-08-08 11:28:25 -060045config TEGRA186_RESET
46 bool "Enable Tegra186 BPMP-based reset driver"
47 depends on TEGRA186_BPMP
48 help
49 Enable support for manipulating Tegra's on-SoC reset signals via IPC
50 requests to the BPMP (Boot and Power Management Processor).
51
Andreas Dannenberg4cfdf4d2018-08-27 15:57:41 +053052config RESET_TI_SCI
53 bool "TI System Control Interface (TI SCI) reset driver"
54 depends on DM_RESET && TI_SCI_PROTOCOL
55 help
56 This enables the reset driver support over TI System Control Interface
57 available on some new TI's SoCs. If you wish to use reset resources
58 managed by the TI System Controller, say Y here. Otherwise, say N.
59
Álvaro Fernández Rojas5161bd32017-05-03 15:10:21 +020060config RESET_BCM6345
61 bool "Reset controller driver for BCM6345"
62 depends on DM_RESET && ARCH_BMIPS
63 help
64 Support reset controller on BCM6345.
65
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +090066config RESET_UNIPHIER
67 bool "Reset controller driver for UniPhier SoCs"
68 depends on ARCH_UNIPHIER
69 default y
70 help
71 Support for reset controllers on UniPhier SoCs.
72 Say Y if you want to control reset signals provided by System Control
73 block, Media I/O block, Peripheral Block.
74
Chia-Wei, Wangb39ef892020-10-15 10:25:14 +080075config RESET_AST2500
maxims@google.com750875c2017-04-17 12:00:24 -070076 bool "Reset controller driver for AST2500 SoCs"
Chia-Wei, Wangacc78362020-10-15 10:25:13 +080077 depends on DM_RESET
maxims@google.com750875c2017-04-17 12:00:24 -070078 default y if ASPEED_AST2500
79 help
Chia-Wei, Wangacc78362020-10-15 10:25:13 +080080 Support for reset controller on AST2500 SoC.
81 Say Y if you want to control reset signals of different peripherals
82 through System Control Unit (SCU).
maxims@google.com750875c2017-04-17 12:00:24 -070083
Chia-Wei, Wang71140512020-12-14 13:54:26 +080084config RESET_AST2600
85 bool "Reset controller driver for AST2600 SoCs"
86 depends on DM_RESET
87 default y if ASPEED_AST2600
88 help
89 Support for reset controller on AST2600 SoC.
90 Say Y if you want to control reset signals of different peripherals
91 through System Control Unit (SCU).
92
Elaine Zhang6e9a3a72017-12-19 18:22:37 +080093config RESET_ROCKCHIP
94 bool "Reset controller driver for Rockchip SoCs"
95 depends on DM_RESET && ARCH_ROCKCHIP && CLK
96 default y
97 help
98 Support for reset controller on rockchip SoC. The main limitation
99 though is that some reset signals, like I2C or MISC reset multiple
100 devices.
101
Eugeniy Paltsev062da422019-10-08 19:29:30 +0300102config RESET_HSDK
103 bool "Synopsys HSDK Reset Driver"
104 depends on DM_RESET && TARGET_HSDK
105 default y
106 help
107 This enables the reset controller driver for HSDK board.
108
Neil Armstrong4f03d6b2018-03-29 14:55:25 +0200109config RESET_MESON
110 bool "Reset controller driver for Amlogic Meson SoCs"
111 depends on DM_RESET && ARCH_MESON
112 imply REGMAP
113 default y
114 help
115 Support for reset controller on Amlogic Meson SoC.
116
Dinh Nguyen5427f5a2018-04-04 17:18:20 -0500117config RESET_SOCFPGA
118 bool "Reset controller driver for SoCFPGA"
119 depends on DM_RESET && ARCH_SOCFPGA
120 default y
121 help
122 Support for reset controller on SoCFPGA platform.
123
developerd48dd9a2018-12-20 16:12:51 +0800124config RESET_MEDIATEK
125 bool "Reset controller driver for MediaTek SoCs"
126 depends on DM_RESET && ARCH_MEDIATEK && CLK
127 default y
128 help
129 Support for reset controller on MediaTek SoCs.
130
developer074393a2019-09-25 17:45:29 +0800131config RESET_MTMIPS
132 bool "Reset controller driver for MediaTek MIPS platform"
133 depends on DM_RESET && ARCH_MTMIPS
134 default y
135 help
136 Support for reset controller on MediaTek MIPS platform.
137
Jagan Teki7f6c2a82019-01-18 22:18:13 +0530138config RESET_SUNXI
139 bool "RESET support for Allwinner SoCs"
140 depends on DM_RESET && ARCH_SUNXI
141 default y
142 help
143 This enables support for common reset driver for
144 Allwinner SoCs.
145
Shawn Guo8aa8f302019-03-20 15:32:39 +0800146config RESET_HISILICON
147 bool "Reset controller driver for HiSilicon SoCs"
148 depends on DM_RESET
149 help
150 Support for reset controller on HiSilicon SoCs.
151
Patrick Wildtdbc644f2019-10-03 16:08:35 +0200152config RESET_IMX7
153 bool "i.MX7/8 Reset Driver"
154 depends on DM_RESET && (ARCH_MX7 || ARCH_IMX8M)
155 default y
156 help
157 Support for reset controller on i.MX7/8 SoCs.
158
Sumit Garg2cf66c452022-08-04 19:57:11 +0530159config RESET_QCOM
160 bool "Reset driver for Qualcomm SoCs"
161 depends on DM_RESET && (ARCH_SNAPDRAGON || ARCH_IPQ40XX)
Robert Markof5edc7a2020-09-10 16:00:02 +0200162 default y
163 help
Sumit Garg2cf66c452022-08-04 19:57:11 +0530164 Support for reset controller on Qualcomm SoCs.
Robert Markof5edc7a2020-09-10 16:00:02 +0200165
Sagar Shrikant Kadam2732b2d2020-07-29 02:36:14 -0700166config RESET_SIFIVE
167 bool "Reset Driver for SiFive SoC's"
Green Wan2e5da522021-05-27 06:52:13 -0700168 depends on DM_RESET && CLK_SIFIVE_PRCI && (TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED)
Sagar Shrikant Kadam2732b2d2020-07-29 02:36:14 -0700169 default y
170 help
171 PRCI module within SiFive SoC's provides mechanism to reset
172 different hw blocks like DDR, gemgxl. With this driver we leverage
173 U-Boot's reset framework to reset these hardware blocks.
174
Yanhong Wangb417f062023-03-29 11:42:11 +0800175config RESET_JH7110
176 bool "Reset driver for StarFive JH7110 SoC"
177 depends on DM_RESET && STARFIVE_JH7110
178 default y
179 help
180 Support for reset controller on StarFive
181 JH7110 SoCs.
182
183config SPL_RESET_JH7110
184 bool "SPL Reset driver for StarFive JH7110 SoC"
185 depends on SPL && STARFIVE_JH7110
186 default y
187 help
188 Support for reset controller on StarFive
189 JH7110 SoCs in SPL.
190
Sean Anderson0c1f6bf2020-06-24 06:41:14 -0400191config RESET_SYSCON
192 bool "Enable generic syscon reset driver support"
193 depends on DM_RESET
194 help
195 Support generic syscon mapped register reset devices.
Nicolas Saenz Julienne057bbbd2020-06-29 18:37:23 +0200196
197config RESET_RASPBERRYPI
198 bool "Raspberry Pi 4 Firmware Reset Controller Driver"
199 depends on DM_RESET && ARCH_BCM283X
200 default USB_XHCI_PCI
201 help
202 Raspberry Pi 4's co-processor controls some of the board's HW
203 initialization process, but it's up to Linux to trigger it when
204 relevant. This driver provides a reset controller capable of
205 interfacing with RPi4's co-processor and model these firmware
206 initialization routines as reset lines.
Etienne Carrierec6e9af32020-09-09 18:44:06 +0200207
208config RESET_SCMI
209 bool "Enable SCMI reset domain driver"
210 select SCMI_FIRMWARE
211 help
212 Enable this option if you want to support reset controller
213 devices exposed by a SCMI agent based on SCMI reset domain
214 protocol communication with a SCMI server.
Michal Simekf0e47692021-07-30 08:00:10 +0200215
216config RESET_ZYNQMP
T Karthik Reddya3a4cc82022-07-20 03:59:57 -0600217 bool "Reset Driver for Xilinx ZynqMP & Versal SoC's"
Michal Simekf0e47692021-07-30 08:00:10 +0200218 depends on DM_RESET && ZYNQMP_FIRMWARE
219 help
T Karthik Reddya3a4cc82022-07-20 03:59:57 -0600220 Support for reset controller on Xilinx ZynqMP & Versal SoC's. Driver
221 is only passing request via Xilinx firmware interface to TF-A and PMU
Michal Simekf0e47692021-07-30 08:00:10 +0200222 firmware.
223
Keerthy0c0bdbb2022-01-27 13:16:51 +0100224config RESET_DRA7
225 bool "Support for TI's DRA7 Reset driver"
226 depends on DM_RESET
227 help
228 Support for TI DRA7-RESET subsystem. Basic Assert/Deassert
229 is supported.
Sergiu Mogabdcfc7d2023-01-04 16:03:18 +0200230
231config RESET_AT91
232 bool "Enable support for Microchip/Atmel Reset Controller driver"
233 depends on DM_RESET && ARCH_AT91
234 help
235 This enables the Reset Controller driver support for Microchip/Atmel
236 SoCs. Mainly used to expose assert/deassert methods to other drivers
237 that require it.
Stephen Warren185ad872016-06-17 09:43:58 -0600238endmenu