| Simon Glass | 8349051 | 2019-12-06 21:42:54 -0700 | [diff] [blame] | 1 | Intel Apollo Lake GPIO controller |
| 2 | |
| 3 | The Apollo Lake (APL) GPIO controller is used to control GPIO functions of |
| 4 | the pins. |
| 5 | |
| 6 | Required properties: |
| 7 | - compatible: "intel,apl-gpio" |
| 8 | - #gpio-cells: Should be 2. The syntax of the gpio specifier used by client |
| 9 | nodes should be the following with values derived from the SoC user manual. |
| 10 | <[phandle of the gpio controller node] |
| 11 | [pin number within the gpio controller] |
| 12 | [flags]> |
| 13 | |
| 14 | Values for gpio specifier: |
| 15 | - Pin number: is a GPIO pin number between 0 and 244 |
| 16 | - Flags: GPIO_ACTIVE_HIGH or GPIO_ACTIVE_LOW |
| 17 | |
| 18 | - gpio-controller: Specifies that the node is a gpio controller. |
| 19 | |
| 20 | Example: |
| 21 | |
| 22 | ... |
| 23 | { |
| 24 | p2sb: p2sb@d,0 { |
| 25 | reg = <0x02006810 0 0 0 0>; |
| 26 | compatible = "intel,apl-p2sb"; |
| 27 | early-regs = <IOMAP_P2SB_BAR 0x100000>; |
| 28 | |
| 29 | north { |
| 30 | compatible = "intel,apl-pinctrl"; |
| 31 | intel,p2sb-port-id = <PID_GPIO_N>; |
| 32 | gpio_n: gpio-n { |
| 33 | compatible = "intel,gpio"; |
| 34 | gpio-controller; |
| 35 | #gpio-cells = <2>; |
| 36 | }; |
| 37 | }; |
| 38 | }; |
| 39 | |
| 40 | i2c_2: i2c2@16,2 { |
| 41 | compatible = "intel,apl-i2c", "snps,designware-i2c-pci"; |
| 42 | reg = <0x0200b210 0 0 0 0>; |
| 43 | #address-cells = <1>; |
| 44 | #size-cells = <0>; |
| 45 | clock-frequency = <400000>; |
| 46 | tpm@50 { |
| 47 | reg = <0x50>; |
| 48 | compatible = "google,cr50"; |
| 49 | u-boot,i2c-offset-len = <0>; |
| 50 | ready-gpio = <&gpio_n GPIO_28 GPIO_ACTIVE_LOW>; |
| 51 | }; |
| 52 | }; |
| 53 | |
| 54 | }; |
| 55 | ... |