blob: 35271b20c891e9585cf95bb16ca5e42177a0435b [file] [log] [blame]
Marek Vasut442c0f12018-08-18 15:58:32 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Designware APB Timer driver
4 *
5 * Copyright (C) 2018 Marek Vasut <marex@denx.de>
6 */
7
8#include <common.h>
9#include <dm.h>
10#include <clk.h>
Simon Glass9bc15642020-02-03 07:36:16 -070011#include <malloc.h>
Simon Goldschmidt0b6b82a2019-10-23 22:23:12 +020012#include <reset.h>
Marek Vasut442c0f12018-08-18 15:58:32 +020013#include <timer.h>
Simon Glass9bc15642020-02-03 07:36:16 -070014#include <dm/device_compat.h>
Marek Vasut442c0f12018-08-18 15:58:32 +020015
16#include <asm/io.h>
17#include <asm/arch/timer.h>
18
19#define DW_APB_LOAD_VAL 0x0
20#define DW_APB_CURR_VAL 0x4
21#define DW_APB_CTRL 0x8
22
Marek Vasut442c0f12018-08-18 15:58:32 +020023struct dw_apb_timer_priv {
Simon Goldschmidt0b6b82a2019-10-23 22:23:12 +020024 fdt_addr_t regs;
25 struct reset_ctl_bulk resets;
Marek Vasut442c0f12018-08-18 15:58:32 +020026};
27
28static int dw_apb_timer_get_count(struct udevice *dev, u64 *count)
29{
30 struct dw_apb_timer_priv *priv = dev_get_priv(dev);
31
32 /*
33 * The DW APB counter counts down, but this function
34 * requires the count to be incrementing. Invert the
35 * result.
36 */
Marek Vasut475e99b2019-04-10 13:44:05 +020037 *count = timer_conv_64(~readl(priv->regs + DW_APB_CURR_VAL));
Marek Vasut442c0f12018-08-18 15:58:32 +020038
39 return 0;
40}
41
42static int dw_apb_timer_probe(struct udevice *dev)
43{
44 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
45 struct dw_apb_timer_priv *priv = dev_get_priv(dev);
46 struct clk clk;
47 int ret;
48
Simon Goldschmidt0b6b82a2019-10-23 22:23:12 +020049 ret = reset_get_bulk(dev, &priv->resets);
50 if (ret)
51 dev_warn(dev, "Can't get reset: %d\n", ret);
52 else
53 reset_deassert_bulk(&priv->resets);
54
Marek Vasut442c0f12018-08-18 15:58:32 +020055 ret = clk_get_by_index(dev, 0, &clk);
56 if (ret)
57 return ret;
58
59 uc_priv->clock_rate = clk_get_rate(&clk);
60
61 clk_free(&clk);
62
63 /* init timer */
64 writel(0xffffffff, priv->regs + DW_APB_LOAD_VAL);
65 writel(0xffffffff, priv->regs + DW_APB_CURR_VAL);
66 setbits_le32(priv->regs + DW_APB_CTRL, 0x3);
67
68 return 0;
69}
70
71static int dw_apb_timer_ofdata_to_platdata(struct udevice *dev)
72{
73 struct dw_apb_timer_priv *priv = dev_get_priv(dev);
74
75 priv->regs = dev_read_addr(dev);
76
77 return 0;
78}
79
Simon Goldschmidt0b6b82a2019-10-23 22:23:12 +020080static int dw_apb_timer_remove(struct udevice *dev)
81{
82 struct dw_apb_timer_priv *priv = dev_get_priv(dev);
83
84 return reset_release_bulk(&priv->resets);
85}
86
Marek Vasut442c0f12018-08-18 15:58:32 +020087static const struct timer_ops dw_apb_timer_ops = {
88 .get_count = dw_apb_timer_get_count,
89};
90
91static const struct udevice_id dw_apb_timer_ids[] = {
92 { .compatible = "snps,dw-apb-timer" },
93 {}
94};
95
96U_BOOT_DRIVER(dw_apb_timer) = {
97 .name = "dw_apb_timer",
98 .id = UCLASS_TIMER,
99 .ops = &dw_apb_timer_ops,
100 .probe = dw_apb_timer_probe,
Marek Vasut442c0f12018-08-18 15:58:32 +0200101 .of_match = dw_apb_timer_ids,
102 .ofdata_to_platdata = dw_apb_timer_ofdata_to_platdata,
Simon Goldschmidt0b6b82a2019-10-23 22:23:12 +0200103 .remove = dw_apb_timer_remove,
Marek Vasut442c0f12018-08-18 15:58:32 +0200104 .priv_auto_alloc_size = sizeof(struct dw_apb_timer_priv),
105};