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Peng Fanaeb9c062018-11-20 10:20:00 +00001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2018 NXP
4 */
5
6#ifndef __IMX8M_EVK_H
7#define __IMX8M_EVK_H
8
9#include <linux/sizes.h>
Simon Glassfb64e362020-05-10 11:40:09 -060010#include <linux/stringify.h>
Peng Fanaeb9c062018-11-20 10:20:00 +000011#include <asm/arch/imx-regs.h>
12
Peng Fan7be67ce2020-07-28 17:28:57 +080013#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
14
Peng Fanaeb9c062018-11-20 10:20:00 +000015#define CONFIG_SPL_MAX_SIZE (124 * 1024)
16#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
17#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
18#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
Peng Fanaeb9c062018-11-20 10:20:00 +000019
20#ifdef CONFIG_SPL_BUILD
21/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
Simon Glass1ba1d4e2021-07-10 21:14:28 -060022#define CONFIG_SPL_WATCHDOG
Simon Glass284cb9c2021-07-10 21:14:31 -060023#define CONFIG_SPL_DRIVERS_MISC
Simon Glasse91ac4c2021-07-10 21:14:24 -060024#define CONFIG_SPL_POWER
Simon Glassbccfc2e2021-07-10 21:14:36 -060025#define CONFIG_SPL_I2C
Peng Fanaeb9c062018-11-20 10:20:00 +000026#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
27#define CONFIG_SPL_STACK 0x187FF0
28#define CONFIG_SPL_LIBCOMMON_SUPPORT
29#define CONFIG_SPL_LIBGENERIC_SUPPORT
Simon Glass035939e2021-07-10 21:14:30 -060030#define CONFIG_SPL_GPIO
Simon Glassb58bfe02021-08-08 12:20:09 -060031#define CONFIG_SPL_MMC
Peng Fanaeb9c062018-11-20 10:20:00 +000032#define CONFIG_SPL_BSS_START_ADDR 0x00180000
33#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
34#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
35#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
36#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
Peng Fanaeb9c062018-11-20 10:20:00 +000037
38/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
39#define CONFIG_MALLOC_F_ADDR 0x182000
40/* For RAW image gives a error info not panic */
41#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
42
43#undef CONFIG_DM_MMC
Peng Fanaeb9c062018-11-20 10:20:00 +000044
Peng Fanaeb9c062018-11-20 10:20:00 +000045#define CONFIG_POWER_PFUZE100
46#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
47#endif
48
49#define CONFIG_REMAKE_ELF
50
Peng Fanaeb9c062018-11-20 10:20:00 +000051/* ENET Config */
52/* ENET1 */
53#if defined(CONFIG_CMD_NET)
Peng Fanaeb9c062018-11-20 10:20:00 +000054#define CONFIG_MII
55#define CONFIG_ETHPRIME "FEC"
56
57#define CONFIG_FEC_MXC
58#define CONFIG_FEC_XCV_TYPE RGMII
59#define CONFIG_FEC_MXC_PHYADDR 0
60#define FEC_QUIRK_ENET_MAC
61
62#define CONFIG_PHY_GIGE
63#define IMX_FEC_BASE 0x30BE0000
Peng Fanaeb9c062018-11-20 10:20:00 +000064#endif
65
Alice Guoa349b3b2021-01-14 16:23:23 +080066#ifndef CONFIG_SPL_BUILD
67#define BOOT_TARGET_DEVICES(func) \
68 func(MMC, mmc, 0) \
69 func(MMC, mmc, 1) \
70 func(DHCP, dhcp, na)
71
72#include <config_distro_bootcmd.h>
73#endif
74
Peng Fanaeb9c062018-11-20 10:20:00 +000075/* Initial environment variables */
76#define CONFIG_EXTRA_ENV_SETTINGS \
Alice Guoa349b3b2021-01-14 16:23:23 +080077 BOOTENV \
78 "scriptaddr=0x43500000\0" \
79 "kernel_addr_r=0x40880000\0" \
Peng Fanaeb9c062018-11-20 10:20:00 +000080 "image=Image\0" \
Fabio Estevam21b135a2019-12-11 14:31:03 -030081 "console=ttymxc0,115200\0" \
Peng Fanaeb9c062018-11-20 10:20:00 +000082 "fdt_addr=0x43000000\0" \
Peng Fanaeb9c062018-11-20 10:20:00 +000083 "boot_fdt=try\0" \
Patrick Wildt02548cf2019-10-14 13:19:00 +020084 "fdt_file=imx8mq-evk.dtb\0" \
Peng Fanaeb9c062018-11-20 10:20:00 +000085 "initrd_addr=0x43800000\0" \
Grygorii Tertychnyi4d7cbe52020-08-21 15:39:43 +020086 "bootm_size=0x10000000\0" \
Peng Fanaeb9c062018-11-20 10:20:00 +000087 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
88 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
Peng Fanaeb9c062018-11-20 10:20:00 +000089
90/* Link Definitions */
Peng Fanaeb9c062018-11-20 10:20:00 +000091
92#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
93#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
94#define CONFIG_SYS_INIT_SP_OFFSET \
95 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
96#define CONFIG_SYS_INIT_SP_ADDR \
97 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
98
Peng Fanaeb9c062018-11-20 10:20:00 +000099#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
100
Peng Fanaeb9c062018-11-20 10:20:00 +0000101#define CONFIG_SYS_SDRAM_BASE 0x40000000
102#define PHYS_SDRAM 0x40000000
103#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
104
Peng Fanaeb9c062018-11-20 10:20:00 +0000105#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
106
107/* Monitor Command Prompt */
108#undef CONFIG_SYS_PROMPT
109#define CONFIG_SYS_PROMPT "u-boot=> "
Peng Fanaeb9c062018-11-20 10:20:00 +0000110#define CONFIG_SYS_CBSIZE 1024
111#define CONFIG_SYS_MAXARGS 64
112#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
113#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
114 sizeof(CONFIG_SYS_PROMPT) + 16)
115
116#define CONFIG_IMX_BOOTAUX
117
Peng Fanaeb9c062018-11-20 10:20:00 +0000118#define CONFIG_SYS_FSL_USDHC_NUM 2
119#define CONFIG_SYS_FSL_ESDHC_ADDR 0
120
Peng Fanaeb9c062018-11-20 10:20:00 +0000121#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
122
123#define CONFIG_MXC_GPIO
124
Peng Fanaeb9c062018-11-20 10:20:00 +0000125#define CONFIG_OF_SYSTEM_SETUP
126
Peng Fanaeb9c062018-11-20 10:20:00 +0000127#endif