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git01.mediatek.com / filogic / uboot / 53633a893a06bd5a0c807287d9cc29337806eaf7 / . / src / arm64 / mediatek / mt8183.dtsi
blob: 976dc968b3ca14de97798bd5e823dbf552ca8300 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame^]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 * Erin Lo <erin.lo@mediatek.com>
6 */
7
8#include <dt-bindings/clock/mt8183-clk.h>
9#include <dt-bindings/gce/mt8183-gce.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/memory/mt8183-larb-port.h>
13#include <dt-bindings/power/mt8183-power.h>
14#include <dt-bindings/reset/mt8183-resets.h>
15#include <dt-bindings/phy/phy.h>
16#include <dt-bindings/thermal/thermal.h>
17#include <dt-bindings/pinctrl/mt8183-pinfunc.h>
18
19/ {
20 compatible = "mediatek,mt8183";
21 interrupt-parent = <&sysirq>;
22 #address-cells = <2>;
23 #size-cells = <2>;
24
25 aliases {
26 i2c0 = &i2c0;
27 i2c1 = &i2c1;
28 i2c2 = &i2c2;
29 i2c3 = &i2c3;
30 i2c4 = &i2c4;
31 i2c5 = &i2c5;
32 i2c6 = &i2c6;
33 i2c7 = &i2c7;
34 i2c8 = &i2c8;
35 i2c9 = &i2c9;
36 i2c10 = &i2c10;
37 i2c11 = &i2c11;
38 ovl0 = &ovl0;
39 ovl-2l0 = &ovl_2l0;
40 ovl-2l1 = &ovl_2l1;
41 rdma0 = &rdma0;
42 rdma1 = &rdma1;
43 };
44
45 cluster0_opp: opp-table-cluster0 {
46 compatible = "operating-points-v2";
47 opp-shared;
48 opp0-793000000 {
49 opp-hz = /bits/ 64 <793000000>;
50 opp-microvolt = <650000>;
51 required-opps = <&opp2_00>;
52 };
53 opp0-910000000 {
54 opp-hz = /bits/ 64 <910000000>;
55 opp-microvolt = <687500>;
56 required-opps = <&opp2_01>;
57 };
58 opp0-1014000000 {
59 opp-hz = /bits/ 64 <1014000000>;
60 opp-microvolt = <718750>;
61 required-opps = <&opp2_02>;
62 };
63 opp0-1131000000 {
64 opp-hz = /bits/ 64 <1131000000>;
65 opp-microvolt = <756250>;
66 required-opps = <&opp2_03>;
67 };
68 opp0-1248000000 {
69 opp-hz = /bits/ 64 <1248000000>;
70 opp-microvolt = <800000>;
71 required-opps = <&opp2_04>;
72 };
73 opp0-1326000000 {
74 opp-hz = /bits/ 64 <1326000000>;
75 opp-microvolt = <818750>;
76 required-opps = <&opp2_05>;
77 };
78 opp0-1417000000 {
79 opp-hz = /bits/ 64 <1417000000>;
80 opp-microvolt = <850000>;
81 required-opps = <&opp2_06>;
82 };
83 opp0-1508000000 {
84 opp-hz = /bits/ 64 <1508000000>;
85 opp-microvolt = <868750>;
86 required-opps = <&opp2_07>;
87 };
88 opp0-1586000000 {
89 opp-hz = /bits/ 64 <1586000000>;
90 opp-microvolt = <893750>;
91 required-opps = <&opp2_08>;
92 };
93 opp0-1625000000 {
94 opp-hz = /bits/ 64 <1625000000>;
95 opp-microvolt = <906250>;
96 required-opps = <&opp2_09>;
97 };
98 opp0-1677000000 {
99 opp-hz = /bits/ 64 <1677000000>;
100 opp-microvolt = <931250>;
101 required-opps = <&opp2_10>;
102 };
103 opp0-1716000000 {
104 opp-hz = /bits/ 64 <1716000000>;
105 opp-microvolt = <943750>;
106 required-opps = <&opp2_11>;
107 };
108 opp0-1781000000 {
109 opp-hz = /bits/ 64 <1781000000>;
110 opp-microvolt = <975000>;
111 required-opps = <&opp2_12>;
112 };
113 opp0-1846000000 {
114 opp-hz = /bits/ 64 <1846000000>;
115 opp-microvolt = <1000000>;
116 required-opps = <&opp2_13>;
117 };
118 opp0-1924000000 {
119 opp-hz = /bits/ 64 <1924000000>;
120 opp-microvolt = <1025000>;
121 required-opps = <&opp2_14>;
122 };
123 opp0-1989000000 {
124 opp-hz = /bits/ 64 <1989000000>;
125 opp-microvolt = <1050000>;
126 required-opps = <&opp2_15>;
127 }; };
128
129 cluster1_opp: opp-table-cluster1 {
130 compatible = "operating-points-v2";
131 opp-shared;
132 opp1-793000000 {
133 opp-hz = /bits/ 64 <793000000>;
134 opp-microvolt = <700000>;
135 required-opps = <&opp2_00>;
136 };
137 opp1-910000000 {
138 opp-hz = /bits/ 64 <910000000>;
139 opp-microvolt = <725000>;
140 required-opps = <&opp2_01>;
141 };
142 opp1-1014000000 {
143 opp-hz = /bits/ 64 <1014000000>;
144 opp-microvolt = <750000>;
145 required-opps = <&opp2_02>;
146 };
147 opp1-1131000000 {
148 opp-hz = /bits/ 64 <1131000000>;
149 opp-microvolt = <775000>;
150 required-opps = <&opp2_03>;
151 };
152 opp1-1248000000 {
153 opp-hz = /bits/ 64 <1248000000>;
154 opp-microvolt = <800000>;
155 required-opps = <&opp2_04>;
156 };
157 opp1-1326000000 {
158 opp-hz = /bits/ 64 <1326000000>;
159 opp-microvolt = <825000>;
160 required-opps = <&opp2_05>;
161 };
162 opp1-1417000000 {
163 opp-hz = /bits/ 64 <1417000000>;
164 opp-microvolt = <850000>;
165 required-opps = <&opp2_06>;
166 };
167 opp1-1508000000 {
168 opp-hz = /bits/ 64 <1508000000>;
169 opp-microvolt = <875000>;
170 required-opps = <&opp2_07>;
171 };
172 opp1-1586000000 {
173 opp-hz = /bits/ 64 <1586000000>;
174 opp-microvolt = <900000>;
175 required-opps = <&opp2_08>;
176 };
177 opp1-1625000000 {
178 opp-hz = /bits/ 64 <1625000000>;
179 opp-microvolt = <912500>;
180 required-opps = <&opp2_09>;
181 };
182 opp1-1677000000 {
183 opp-hz = /bits/ 64 <1677000000>;
184 opp-microvolt = <931250>;
185 required-opps = <&opp2_10>;
186 };
187 opp1-1716000000 {
188 opp-hz = /bits/ 64 <1716000000>;
189 opp-microvolt = <950000>;
190 required-opps = <&opp2_11>;
191 };
192 opp1-1781000000 {
193 opp-hz = /bits/ 64 <1781000000>;
194 opp-microvolt = <975000>;
195 required-opps = <&opp2_12>;
196 };
197 opp1-1846000000 {
198 opp-hz = /bits/ 64 <1846000000>;
199 opp-microvolt = <1000000>;
200 required-opps = <&opp2_13>;
201 };
202 opp1-1924000000 {
203 opp-hz = /bits/ 64 <1924000000>;
204 opp-microvolt = <1025000>;
205 required-opps = <&opp2_14>;
206 };
207 opp1-1989000000 {
208 opp-hz = /bits/ 64 <1989000000>;
209 opp-microvolt = <1050000>;
210 required-opps = <&opp2_15>;
211 };
212 };
213
214 cci_opp: opp-table-cci {
215 compatible = "operating-points-v2";
216 opp-shared;
217 opp2_00: opp-273000000 {
218 opp-hz = /bits/ 64 <273000000>;
219 opp-microvolt = <650000>;
220 };
221 opp2_01: opp-338000000 {
222 opp-hz = /bits/ 64 <338000000>;
223 opp-microvolt = <687500>;
224 };
225 opp2_02: opp-403000000 {
226 opp-hz = /bits/ 64 <403000000>;
227 opp-microvolt = <718750>;
228 };
229 opp2_03: opp-463000000 {
230 opp-hz = /bits/ 64 <463000000>;
231 opp-microvolt = <756250>;
232 };
233 opp2_04: opp-546000000 {
234 opp-hz = /bits/ 64 <546000000>;
235 opp-microvolt = <800000>;
236 };
237 opp2_05: opp-624000000 {
238 opp-hz = /bits/ 64 <624000000>;
239 opp-microvolt = <818750>;
240 };
241 opp2_06: opp-689000000 {
242 opp-hz = /bits/ 64 <689000000>;
243 opp-microvolt = <850000>;
244 };
245 opp2_07: opp-767000000 {
246 opp-hz = /bits/ 64 <767000000>;
247 opp-microvolt = <868750>;
248 };
249 opp2_08: opp-845000000 {
250 opp-hz = /bits/ 64 <845000000>;
251 opp-microvolt = <893750>;
252 };
253 opp2_09: opp-871000000 {
254 opp-hz = /bits/ 64 <871000000>;
255 opp-microvolt = <906250>;
256 };
257 opp2_10: opp-923000000 {
258 opp-hz = /bits/ 64 <923000000>;
259 opp-microvolt = <931250>;
260 };
261 opp2_11: opp-962000000 {
262 opp-hz = /bits/ 64 <962000000>;
263 opp-microvolt = <943750>;
264 };
265 opp2_12: opp-1027000000 {
266 opp-hz = /bits/ 64 <1027000000>;
267 opp-microvolt = <975000>;
268 };
269 opp2_13: opp-1092000000 {
270 opp-hz = /bits/ 64 <1092000000>;
271 opp-microvolt = <1000000>;
272 };
273 opp2_14: opp-1144000000 {
274 opp-hz = /bits/ 64 <1144000000>;
275 opp-microvolt = <1025000>;
276 };
277 opp2_15: opp-1196000000 {
278 opp-hz = /bits/ 64 <1196000000>;
279 opp-microvolt = <1050000>;
280 };
281 };
282
283 cci: cci {
284 compatible = "mediatek,mt8183-cci";
285 clocks = <&mcucfg CLK_MCU_BUS_SEL>,
286 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
287 clock-names = "cci", "intermediate";
288 operating-points-v2 = <&cci_opp>;
289 };
290
291 cpus {
292 #address-cells = <1>;
293 #size-cells = <0>;
294
295 cpu-map {
296 cluster0 {
297 core0 {
298 cpu = <&cpu0>;
299 };
300 core1 {
301 cpu = <&cpu1>;
302 };
303 core2 {
304 cpu = <&cpu2>;
305 };
306 core3 {
307 cpu = <&cpu3>;
308 };
309 };
310
311 cluster1 {
312 core0 {
313 cpu = <&cpu4>;
314 };
315 core1 {
316 cpu = <&cpu5>;
317 };
318 core2 {
319 cpu = <&cpu6>;
320 };
321 core3 {
322 cpu = <&cpu7>;
323 };
324 };
325 };
326
327 cpu0: cpu@0 {
328 device_type = "cpu";
329 compatible = "arm,cortex-a53";
330 reg = <0x000>;
331 enable-method = "psci";
332 capacity-dmips-mhz = <741>;
333 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
334 clocks = <&mcucfg CLK_MCU_MP0_SEL>,
335 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
336 clock-names = "cpu", "intermediate";
337 operating-points-v2 = <&cluster0_opp>;
338 dynamic-power-coefficient = <84>;
339 i-cache-size = <32768>;
340 i-cache-line-size = <64>;
341 i-cache-sets = <256>;
342 d-cache-size = <32768>;
343 d-cache-line-size = <64>;
344 d-cache-sets = <128>;
345 next-level-cache = <&l2_0>;
346 #cooling-cells = <2>;
347 mediatek,cci = <&cci>;
348 };
349
350 cpu1: cpu@1 {
351 device_type = "cpu";
352 compatible = "arm,cortex-a53";
353 reg = <0x001>;
354 enable-method = "psci";
355 capacity-dmips-mhz = <741>;
356 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
357 clocks = <&mcucfg CLK_MCU_MP0_SEL>,
358 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
359 clock-names = "cpu", "intermediate";
360 operating-points-v2 = <&cluster0_opp>;
361 dynamic-power-coefficient = <84>;
362 i-cache-size = <32768>;
363 i-cache-line-size = <64>;
364 i-cache-sets = <256>;
365 d-cache-size = <32768>;
366 d-cache-line-size = <64>;
367 d-cache-sets = <128>;
368 next-level-cache = <&l2_0>;
369 #cooling-cells = <2>;
370 mediatek,cci = <&cci>;
371 };
372
373 cpu2: cpu@2 {
374 device_type = "cpu";
375 compatible = "arm,cortex-a53";
376 reg = <0x002>;
377 enable-method = "psci";
378 capacity-dmips-mhz = <741>;
379 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
380 clocks = <&mcucfg CLK_MCU_MP0_SEL>,
381 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
382 clock-names = "cpu", "intermediate";
383 operating-points-v2 = <&cluster0_opp>;
384 dynamic-power-coefficient = <84>;
385 i-cache-size = <32768>;
386 i-cache-line-size = <64>;
387 i-cache-sets = <256>;
388 d-cache-size = <32768>;
389 d-cache-line-size = <64>;
390 d-cache-sets = <128>;
391 next-level-cache = <&l2_0>;
392 #cooling-cells = <2>;
393 mediatek,cci = <&cci>;
394 };
395
396 cpu3: cpu@3 {
397 device_type = "cpu";
398 compatible = "arm,cortex-a53";
399 reg = <0x003>;
400 enable-method = "psci";
401 capacity-dmips-mhz = <741>;
402 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
403 clocks = <&mcucfg CLK_MCU_MP0_SEL>,
404 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
405 clock-names = "cpu", "intermediate";
406 operating-points-v2 = <&cluster0_opp>;
407 dynamic-power-coefficient = <84>;
408 i-cache-size = <32768>;
409 i-cache-line-size = <64>;
410 i-cache-sets = <256>;
411 d-cache-size = <32768>;
412 d-cache-line-size = <64>;
413 d-cache-sets = <128>;
414 next-level-cache = <&l2_0>;
415 #cooling-cells = <2>;
416 mediatek,cci = <&cci>;
417 };
418
419 cpu4: cpu@100 {
420 device_type = "cpu";
421 compatible = "arm,cortex-a73";
422 reg = <0x100>;
423 enable-method = "psci";
424 capacity-dmips-mhz = <1024>;
425 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
426 clocks = <&mcucfg CLK_MCU_MP2_SEL>,
427 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
428 clock-names = "cpu", "intermediate";
429 operating-points-v2 = <&cluster1_opp>;
430 dynamic-power-coefficient = <211>;
431 i-cache-size = <65536>;
432 i-cache-line-size = <64>;
433 i-cache-sets = <256>;
434 d-cache-size = <65536>;
435 d-cache-line-size = <64>;
436 d-cache-sets = <256>;
437 next-level-cache = <&l2_1>;
438 #cooling-cells = <2>;
439 mediatek,cci = <&cci>;
440 };
441
442 cpu5: cpu@101 {
443 device_type = "cpu";
444 compatible = "arm,cortex-a73";
445 reg = <0x101>;
446 enable-method = "psci";
447 capacity-dmips-mhz = <1024>;
448 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
449 clocks = <&mcucfg CLK_MCU_MP2_SEL>,
450 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
451 clock-names = "cpu", "intermediate";
452 operating-points-v2 = <&cluster1_opp>;
453 dynamic-power-coefficient = <211>;
454 i-cache-size = <65536>;
455 i-cache-line-size = <64>;
456 i-cache-sets = <256>;
457 d-cache-size = <65536>;
458 d-cache-line-size = <64>;
459 d-cache-sets = <256>;
460 next-level-cache = <&l2_1>;
461 #cooling-cells = <2>;
462 mediatek,cci = <&cci>;
463 };
464
465 cpu6: cpu@102 {
466 device_type = "cpu";
467 compatible = "arm,cortex-a73";
468 reg = <0x102>;
469 enable-method = "psci";
470 capacity-dmips-mhz = <1024>;
471 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
472 clocks = <&mcucfg CLK_MCU_MP2_SEL>,
473 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
474 clock-names = "cpu", "intermediate";
475 operating-points-v2 = <&cluster1_opp>;
476 dynamic-power-coefficient = <211>;
477 i-cache-size = <65536>;
478 i-cache-line-size = <64>;
479 i-cache-sets = <256>;
480 d-cache-size = <65536>;
481 d-cache-line-size = <64>;
482 d-cache-sets = <256>;
483 next-level-cache = <&l2_1>;
484 #cooling-cells = <2>;
485 mediatek,cci = <&cci>;
486 };
487
488 cpu7: cpu@103 {
489 device_type = "cpu";
490 compatible = "arm,cortex-a73";
491 reg = <0x103>;
492 enable-method = "psci";
493 capacity-dmips-mhz = <1024>;
494 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
495 clocks = <&mcucfg CLK_MCU_MP2_SEL>,
496 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
497 clock-names = "cpu", "intermediate";
498 operating-points-v2 = <&cluster1_opp>;
499 dynamic-power-coefficient = <211>;
500 i-cache-size = <65536>;
501 i-cache-line-size = <64>;
502 i-cache-sets = <256>;
503 d-cache-size = <65536>;
504 d-cache-line-size = <64>;
505 d-cache-sets = <256>;
506 next-level-cache = <&l2_1>;
507 #cooling-cells = <2>;
508 mediatek,cci = <&cci>;
509 };
510
511 idle-states {
512 entry-method = "psci";
513
514 CPU_SLEEP: cpu-sleep {
515 compatible = "arm,idle-state";
516 local-timer-stop;
517 arm,psci-suspend-param = <0x00010001>;
518 entry-latency-us = <200>;
519 exit-latency-us = <200>;
520 min-residency-us = <800>;
521 };
522
523 CLUSTER_SLEEP0: cluster-sleep-0 {
524 compatible = "arm,idle-state";
525 local-timer-stop;
526 arm,psci-suspend-param = <0x01010001>;
527 entry-latency-us = <250>;
528 exit-latency-us = <400>;
529 min-residency-us = <1000>;
530 };
531 CLUSTER_SLEEP1: cluster-sleep-1 {
532 compatible = "arm,idle-state";
533 local-timer-stop;
534 arm,psci-suspend-param = <0x01010001>;
535 entry-latency-us = <250>;
536 exit-latency-us = <400>;
537 min-residency-us = <1300>;
538 };
539 };
540
541 l2_0: l2-cache0 {
542 compatible = "cache";
543 cache-level = <2>;
544 cache-size = <1048576>;
545 cache-line-size = <64>;
546 cache-sets = <1024>;
547 cache-unified;
548 };
549
550 l2_1: l2-cache1 {
551 compatible = "cache";
552 cache-level = <2>;
553 cache-size = <1048576>;
554 cache-line-size = <64>;
555 cache-sets = <1024>;
556 cache-unified;
557 };
558 };
559
560 gpu_opp_table: opp-table-0 {
561 compatible = "operating-points-v2";
562 opp-shared;
563
564 opp-300000000 {
565 opp-hz = /bits/ 64 <300000000>;
566 opp-microvolt = <625000>;
567 };
568
569 opp-320000000 {
570 opp-hz = /bits/ 64 <320000000>;
571 opp-microvolt = <631250>;
572 };
573
574 opp-340000000 {
575 opp-hz = /bits/ 64 <340000000>;
576 opp-microvolt = <637500>;
577 };
578
579 opp-360000000 {
580 opp-hz = /bits/ 64 <360000000>;
581 opp-microvolt = <643750>;
582 };
583
584 opp-380000000 {
585 opp-hz = /bits/ 64 <380000000>;
586 opp-microvolt = <650000>;
587 };
588
589 opp-400000000 {
590 opp-hz = /bits/ 64 <400000000>;
591 opp-microvolt = <656250>;
592 };
593
594 opp-420000000 {
595 opp-hz = /bits/ 64 <420000000>;
596 opp-microvolt = <662500>;
597 };
598
599 opp-460000000 {
600 opp-hz = /bits/ 64 <460000000>;
601 opp-microvolt = <675000>;
602 };
603
604 opp-500000000 {
605 opp-hz = /bits/ 64 <500000000>;
606 opp-microvolt = <687500>;
607 };
608
609 opp-540000000 {
610 opp-hz = /bits/ 64 <540000000>;
611 opp-microvolt = <700000>;
612 };
613
614 opp-580000000 {
615 opp-hz = /bits/ 64 <580000000>;
616 opp-microvolt = <712500>;
617 };
618
619 opp-620000000 {
620 opp-hz = /bits/ 64 <620000000>;
621 opp-microvolt = <725000>;
622 };
623
624 opp-653000000 {
625 opp-hz = /bits/ 64 <653000000>;
626 opp-microvolt = <743750>;
627 };
628
629 opp-698000000 {
630 opp-hz = /bits/ 64 <698000000>;
631 opp-microvolt = <768750>;
632 };
633
634 opp-743000000 {
635 opp-hz = /bits/ 64 <743000000>;
636 opp-microvolt = <793750>;
637 };
638
639 opp-800000000 {
640 opp-hz = /bits/ 64 <800000000>;
641 opp-microvolt = <825000>;
642 };
643 };
644
645 pmu-a53 {
646 compatible = "arm,cortex-a53-pmu";
647 interrupt-parent = <&gic>;
648 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
649 };
650
651 pmu-a73 {
652 compatible = "arm,cortex-a73-pmu";
653 interrupt-parent = <&gic>;
654 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
655 };
656
657 psci {
658 compatible = "arm,psci-1.0";
659 method = "smc";
660 };
661
662 clk13m: fixed-factor-clock-13m {
663 compatible = "fixed-factor-clock";
664 #clock-cells = <0>;
665 clocks = <&clk26m>;
666 clock-div = <2>;
667 clock-mult = <1>;
668 clock-output-names = "clk13m";
669 };
670
671 clk26m: oscillator {
672 compatible = "fixed-clock";
673 #clock-cells = <0>;
674 clock-frequency = <26000000>;
675 clock-output-names = "clk26m";
676 };
677
678 timer {
679 compatible = "arm,armv8-timer";
680 interrupt-parent = <&gic>;
681 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
682 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
683 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
684 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
685 };
686
687 soc {
688 #address-cells = <2>;
689 #size-cells = <2>;
690 compatible = "simple-bus";
691 ranges;
692
693 soc_data: efuse@8000000 {
694 compatible = "mediatek,mt8183-efuse",
695 "mediatek,efuse";
696 reg = <0 0x08000000 0 0x0010>;
697 #address-cells = <1>;
698 #size-cells = <1>;
699 status = "disabled";
700 };
701
702 gic: interrupt-controller@c000000 {
703 compatible = "arm,gic-v3";
704 #interrupt-cells = <4>;
705 interrupt-parent = <&gic>;
706 interrupt-controller;
707 reg = <0 0x0c000000 0 0x40000>, /* GICD */
708 <0 0x0c100000 0 0x200000>, /* GICR */
709 <0 0x0c400000 0 0x2000>, /* GICC */
710 <0 0x0c410000 0 0x1000>, /* GICH */
711 <0 0x0c420000 0 0x2000>; /* GICV */
712
713 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
714 ppi-partitions {
715 ppi_cluster0: interrupt-partition-0 {
716 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
717 };
718 ppi_cluster1: interrupt-partition-1 {
719 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
720 };
721 };
722 };
723
724 mcucfg: syscon@c530000 {
725 compatible = "mediatek,mt8183-mcucfg", "syscon";
726 reg = <0 0x0c530000 0 0x1000>;
727 #clock-cells = <1>;
728 };
729
730 sysirq: interrupt-controller@c530a80 {
731 compatible = "mediatek,mt8183-sysirq",
732 "mediatek,mt6577-sysirq";
733 interrupt-controller;
734 #interrupt-cells = <3>;
735 interrupt-parent = <&gic>;
736 reg = <0 0x0c530a80 0 0x50>;
737 };
738
739 cpu_debug0: cpu-debug@d410000 {
740 compatible = "arm,coresight-cpu-debug", "arm,primecell";
741 reg = <0x0 0xd410000 0x0 0x1000>;
742 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
743 clock-names = "apb_pclk";
744 cpu = <&cpu0>;
745 };
746
747 cpu_debug1: cpu-debug@d510000 {
748 compatible = "arm,coresight-cpu-debug", "arm,primecell";
749 reg = <0x0 0xd510000 0x0 0x1000>;
750 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
751 clock-names = "apb_pclk";
752 cpu = <&cpu1>;
753 };
754
755 cpu_debug2: cpu-debug@d610000 {
756 compatible = "arm,coresight-cpu-debug", "arm,primecell";
757 reg = <0x0 0xd610000 0x0 0x1000>;
758 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
759 clock-names = "apb_pclk";
760 cpu = <&cpu2>;
761 };
762
763 cpu_debug3: cpu-debug@d710000 {
764 compatible = "arm,coresight-cpu-debug", "arm,primecell";
765 reg = <0x0 0xd710000 0x0 0x1000>;
766 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
767 clock-names = "apb_pclk";
768 cpu = <&cpu3>;
769 };
770
771 cpu_debug4: cpu-debug@d810000 {
772 compatible = "arm,coresight-cpu-debug", "arm,primecell";
773 reg = <0x0 0xd810000 0x0 0x1000>;
774 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
775 clock-names = "apb_pclk";
776 cpu = <&cpu4>;
777 };
778
779 cpu_debug5: cpu-debug@d910000 {
780 compatible = "arm,coresight-cpu-debug", "arm,primecell";
781 reg = <0x0 0xd910000 0x0 0x1000>;
782 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
783 clock-names = "apb_pclk";
784 cpu = <&cpu5>;
785 };
786
787 cpu_debug6: cpu-debug@da10000 {
788 compatible = "arm,coresight-cpu-debug", "arm,primecell";
789 reg = <0x0 0xda10000 0x0 0x1000>;
790 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
791 clock-names = "apb_pclk";
792 cpu = <&cpu6>;
793 };
794
795 cpu_debug7: cpu-debug@db10000 {
796 compatible = "arm,coresight-cpu-debug", "arm,primecell";
797 reg = <0x0 0xdb10000 0x0 0x1000>;
798 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
799 clock-names = "apb_pclk";
800 cpu = <&cpu7>;
801 };
802
803 topckgen: syscon@10000000 {
804 compatible = "mediatek,mt8183-topckgen", "syscon";
805 reg = <0 0x10000000 0 0x1000>;
806 #clock-cells = <1>;
807 };
808
809 infracfg: syscon@10001000 {
810 compatible = "mediatek,mt8183-infracfg", "syscon";
811 reg = <0 0x10001000 0 0x1000>;
812 #clock-cells = <1>;
813 #reset-cells = <1>;
814 };
815
816 pericfg: syscon@10003000 {
817 compatible = "mediatek,mt8183-pericfg", "syscon";
818 reg = <0 0x10003000 0 0x1000>;
819 #clock-cells = <1>;
820 };
821
822 pio: pinctrl@10005000 {
823 compatible = "mediatek,mt8183-pinctrl";
824 reg = <0 0x10005000 0 0x1000>,
825 <0 0x11f20000 0 0x1000>,
826 <0 0x11e80000 0 0x1000>,
827 <0 0x11e70000 0 0x1000>,
828 <0 0x11e90000 0 0x1000>,
829 <0 0x11d30000 0 0x1000>,
830 <0 0x11d20000 0 0x1000>,
831 <0 0x11c50000 0 0x1000>,
832 <0 0x11f30000 0 0x1000>,
833 <0 0x1000b000 0 0x1000>;
834 reg-names = "iocfg0", "iocfg1", "iocfg2",
835 "iocfg3", "iocfg4", "iocfg5",
836 "iocfg6", "iocfg7", "iocfg8",
837 "eint";
838 gpio-controller;
839 #gpio-cells = <2>;
840 gpio-ranges = <&pio 0 0 192>;
841 interrupt-controller;
842 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
843 #interrupt-cells = <2>;
844 };
845
846 scpsys: syscon@10006000 {
847 compatible = "mediatek,mt8183-scpsys", "syscon", "simple-mfd";
848 reg = <0 0x10006000 0 0x1000>;
849
850 /* System Power Manager */
851 spm: power-controller {
852 compatible = "mediatek,mt8183-power-controller";
853 #address-cells = <1>;
854 #size-cells = <0>;
855 #power-domain-cells = <1>;
856
857 /* power domain of the SoC */
858 power-domain@MT8183_POWER_DOMAIN_AUDIO {
859 reg = <MT8183_POWER_DOMAIN_AUDIO>;
860 clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
861 <&infracfg CLK_INFRA_AUDIO>,
862 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>;
863 clock-names = "audio", "audio1", "audio2";
864 #power-domain-cells = <0>;
865 };
866
867 power-domain@MT8183_POWER_DOMAIN_CONN {
868 reg = <MT8183_POWER_DOMAIN_CONN>;
869 mediatek,infracfg = <&infracfg>;
870 #power-domain-cells = <0>;
871 };
872
873 mfg_async: power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC {
874 reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>;
875 clocks = <&topckgen CLK_TOP_MUX_MFG>;
876 clock-names = "mfg";
877 #address-cells = <1>;
878 #size-cells = <0>;
879 #power-domain-cells = <1>;
880
881 mfg: power-domain@MT8183_POWER_DOMAIN_MFG {
882 reg = <MT8183_POWER_DOMAIN_MFG>;
883 #address-cells = <1>;
884 #size-cells = <0>;
885 #power-domain-cells = <1>;
886
887 power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 {
888 reg = <MT8183_POWER_DOMAIN_MFG_CORE0>;
889 #power-domain-cells = <0>;
890 };
891
892 power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 {
893 reg = <MT8183_POWER_DOMAIN_MFG_CORE1>;
894 #power-domain-cells = <0>;
895 };
896
897 power-domain@MT8183_POWER_DOMAIN_MFG_2D {
898 reg = <MT8183_POWER_DOMAIN_MFG_2D>;
899 mediatek,infracfg = <&infracfg>;
900 #power-domain-cells = <0>;
901 };
902 };
903 };
904
905 power-domain@MT8183_POWER_DOMAIN_DISP {
906 reg = <MT8183_POWER_DOMAIN_DISP>;
907 clocks = <&topckgen CLK_TOP_MUX_MM>,
908 <&mmsys CLK_MM_SMI_COMMON>,
909 <&mmsys CLK_MM_SMI_LARB0>,
910 <&mmsys CLK_MM_SMI_LARB1>,
911 <&mmsys CLK_MM_GALS_COMM0>,
912 <&mmsys CLK_MM_GALS_COMM1>,
913 <&mmsys CLK_MM_GALS_CCU2MM>,
914 <&mmsys CLK_MM_GALS_IPU12MM>,
915 <&mmsys CLK_MM_GALS_IMG2MM>,
916 <&mmsys CLK_MM_GALS_CAM2MM>,
917 <&mmsys CLK_MM_GALS_IPU2MM>;
918 clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3",
919 "mm-4", "mm-5", "mm-6", "mm-7",
920 "mm-8", "mm-9";
921 mediatek,infracfg = <&infracfg>;
922 mediatek,smi = <&smi_common>;
923 #address-cells = <1>;
924 #size-cells = <0>;
925 #power-domain-cells = <1>;
926
927 power-domain@MT8183_POWER_DOMAIN_CAM {
928 reg = <MT8183_POWER_DOMAIN_CAM>;
929 clocks = <&topckgen CLK_TOP_MUX_CAM>,
930 <&camsys CLK_CAM_LARB6>,
931 <&camsys CLK_CAM_LARB3>,
932 <&camsys CLK_CAM_SENINF>,
933 <&camsys CLK_CAM_CAMSV0>,
934 <&camsys CLK_CAM_CAMSV1>,
935 <&camsys CLK_CAM_CAMSV2>,
936 <&camsys CLK_CAM_CCU>;
937 clock-names = "cam", "cam-0", "cam-1",
938 "cam-2", "cam-3", "cam-4",
939 "cam-5", "cam-6";
940 mediatek,infracfg = <&infracfg>;
941 mediatek,smi = <&smi_common>;
942 #power-domain-cells = <0>;
943 };
944
945 power-domain@MT8183_POWER_DOMAIN_ISP {
946 reg = <MT8183_POWER_DOMAIN_ISP>;
947 clocks = <&topckgen CLK_TOP_MUX_IMG>,
948 <&imgsys CLK_IMG_LARB5>,
949 <&imgsys CLK_IMG_LARB2>;
950 clock-names = "isp", "isp-0", "isp-1";
951 mediatek,infracfg = <&infracfg>;
952 mediatek,smi = <&smi_common>;
953 #power-domain-cells = <0>;
954 };
955
956 power-domain@MT8183_POWER_DOMAIN_VDEC {
957 reg = <MT8183_POWER_DOMAIN_VDEC>;
958 mediatek,smi = <&smi_common>;
959 #power-domain-cells = <0>;
960 };
961
962 power-domain@MT8183_POWER_DOMAIN_VENC {
963 reg = <MT8183_POWER_DOMAIN_VENC>;
964 mediatek,smi = <&smi_common>;
965 #power-domain-cells = <0>;
966 };
967
968 power-domain@MT8183_POWER_DOMAIN_VPU_TOP {
969 reg = <MT8183_POWER_DOMAIN_VPU_TOP>;
970 clocks = <&topckgen CLK_TOP_MUX_IPU_IF>,
971 <&topckgen CLK_TOP_MUX_DSP>,
972 <&ipu_conn CLK_IPU_CONN_IPU>,
973 <&ipu_conn CLK_IPU_CONN_AHB>,
974 <&ipu_conn CLK_IPU_CONN_AXI>,
975 <&ipu_conn CLK_IPU_CONN_ISP>,
976 <&ipu_conn CLK_IPU_CONN_CAM_ADL>,
977 <&ipu_conn CLK_IPU_CONN_IMG_ADL>;
978 clock-names = "vpu", "vpu1", "vpu-0", "vpu-1",
979 "vpu-2", "vpu-3", "vpu-4", "vpu-5";
980 mediatek,infracfg = <&infracfg>;
981 mediatek,smi = <&smi_common>;
982 #address-cells = <1>;
983 #size-cells = <0>;
984 #power-domain-cells = <1>;
985
986 power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 {
987 reg = <MT8183_POWER_DOMAIN_VPU_CORE0>;
988 clocks = <&topckgen CLK_TOP_MUX_DSP1>;
989 clock-names = "vpu2";
990 mediatek,infracfg = <&infracfg>;
991 #power-domain-cells = <0>;
992 };
993
994 power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 {
995 reg = <MT8183_POWER_DOMAIN_VPU_CORE1>;
996 clocks = <&topckgen CLK_TOP_MUX_DSP2>;
997 clock-names = "vpu3";
998 mediatek,infracfg = <&infracfg>;
999 #power-domain-cells = <0>;
1000 };
1001 };
1002 };
1003 };
1004 };
1005
1006 watchdog: watchdog@10007000 {
1007 compatible = "mediatek,mt8183-wdt";
1008 reg = <0 0x10007000 0 0x100>;
1009 #reset-cells = <1>;
1010 };
1011
1012 apmixedsys: syscon@1000c000 {
1013 compatible = "mediatek,mt8183-apmixedsys", "syscon";
1014 reg = <0 0x1000c000 0 0x1000>;
1015 #clock-cells = <1>;
1016 };
1017
1018 pwrap: pwrap@1000d000 {
1019 compatible = "mediatek,mt8183-pwrap";
1020 reg = <0 0x1000d000 0 0x1000>;
1021 reg-names = "pwrap";
1022 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
1023 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
1024 <&infracfg CLK_INFRA_PMIC_AP>;
1025 clock-names = "spi", "wrap";
1026 };
1027
1028 keyboard: keyboard@10010000 {
1029 compatible = "mediatek,mt6779-keypad";
1030 reg = <0 0x10010000 0 0x1000>;
1031 interrupts = <GIC_SPI 186 IRQ_TYPE_EDGE_FALLING>;
1032 clocks = <&clk26m>;
1033 clock-names = "kpd";
1034 status = "disabled";
1035 };
1036
1037 scp: scp@10500000 {
1038 compatible = "mediatek,mt8183-scp";
1039 reg = <0 0x10500000 0 0x80000>,
1040 <0 0x105c0000 0 0x19080>;
1041 reg-names = "sram", "cfg";
1042 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1043 clocks = <&infracfg CLK_INFRA_SCPSYS>;
1044 clock-names = "main";
1045 memory-region = <&scp_mem_reserved>;
1046 status = "disabled";
1047 };
1048
1049 systimer: timer@10017000 {
1050 compatible = "mediatek,mt8183-timer",
1051 "mediatek,mt6765-timer";
1052 reg = <0 0x10017000 0 0x1000>;
1053 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
1054 clocks = <&clk13m>;
1055 };
1056
1057 iommu: iommu@10205000 {
1058 compatible = "mediatek,mt8183-m4u";
1059 reg = <0 0x10205000 0 0x1000>;
1060 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
1061 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>,
1062 <&larb4>, <&larb5>, <&larb6>;
1063 #iommu-cells = <1>;
1064 };
1065
1066 gce: mailbox@10238000 {
1067 compatible = "mediatek,mt8183-gce";
1068 reg = <0 0x10238000 0 0x4000>;
1069 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
1070 #mbox-cells = <2>;
1071 clocks = <&infracfg CLK_INFRA_GCE>;
1072 clock-names = "gce";
1073 };
1074
1075 auxadc: auxadc@11001000 {
1076 compatible = "mediatek,mt8183-auxadc",
1077 "mediatek,mt8173-auxadc";
1078 reg = <0 0x11001000 0 0x1000>;
1079 clocks = <&infracfg CLK_INFRA_AUXADC>;
1080 clock-names = "main";
1081 #io-channel-cells = <1>;
1082 status = "disabled";
1083 };
1084
1085 uart0: serial@11002000 {
1086 compatible = "mediatek,mt8183-uart",
1087 "mediatek,mt6577-uart";
1088 reg = <0 0x11002000 0 0x1000>;
1089 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
1090 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
1091 clock-names = "baud", "bus";
1092 status = "disabled";
1093 };
1094
1095 uart1: serial@11003000 {
1096 compatible = "mediatek,mt8183-uart",
1097 "mediatek,mt6577-uart";
1098 reg = <0 0x11003000 0 0x1000>;
1099 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
1100 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
1101 clock-names = "baud", "bus";
1102 status = "disabled";
1103 };
1104
1105 uart2: serial@11004000 {
1106 compatible = "mediatek,mt8183-uart",
1107 "mediatek,mt6577-uart";
1108 reg = <0 0x11004000 0 0x1000>;
1109 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
1110 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
1111 clock-names = "baud", "bus";
1112 status = "disabled";
1113 };
1114
1115 i2c6: i2c@11005000 {
1116 compatible = "mediatek,mt8183-i2c";
1117 reg = <0 0x11005000 0 0x1000>,
1118 <0 0x11000600 0 0x80>;
1119 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
1120 clocks = <&infracfg CLK_INFRA_I2C6>,
1121 <&infracfg CLK_INFRA_AP_DMA>;
1122 clock-names = "main", "dma";
1123 clock-div = <1>;
1124 #address-cells = <1>;
1125 #size-cells = <0>;
1126 status = "disabled";
1127 };
1128
1129 i2c0: i2c@11007000 {
1130 compatible = "mediatek,mt8183-i2c";
1131 reg = <0 0x11007000 0 0x1000>,
1132 <0 0x11000080 0 0x80>;
1133 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
1134 clocks = <&infracfg CLK_INFRA_I2C0>,
1135 <&infracfg CLK_INFRA_AP_DMA>;
1136 clock-names = "main", "dma";
1137 clock-div = <1>;
1138 #address-cells = <1>;
1139 #size-cells = <0>;
1140 status = "disabled";
1141 };
1142
1143 i2c4: i2c@11008000 {
1144 compatible = "mediatek,mt8183-i2c";
1145 reg = <0 0x11008000 0 0x1000>,
1146 <0 0x11000100 0 0x80>;
1147 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
1148 clocks = <&infracfg CLK_INFRA_I2C1>,
1149 <&infracfg CLK_INFRA_AP_DMA>,
1150 <&infracfg CLK_INFRA_I2C1_ARBITER>;
1151 clock-names = "main", "dma","arb";
1152 clock-div = <1>;
1153 #address-cells = <1>;
1154 #size-cells = <0>;
1155 status = "disabled";
1156 };
1157
1158 i2c2: i2c@11009000 {
1159 compatible = "mediatek,mt8183-i2c";
1160 reg = <0 0x11009000 0 0x1000>,
1161 <0 0x11000280 0 0x80>;
1162 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
1163 clocks = <&infracfg CLK_INFRA_I2C2>,
1164 <&infracfg CLK_INFRA_AP_DMA>,
1165 <&infracfg CLK_INFRA_I2C2_ARBITER>;
1166 clock-names = "main", "dma", "arb";
1167 clock-div = <1>;
1168 #address-cells = <1>;
1169 #size-cells = <0>;
1170 status = "disabled";
1171 };
1172
1173 spi0: spi@1100a000 {
1174 compatible = "mediatek,mt8183-spi";
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1177 reg = <0 0x1100a000 0 0x1000>;
1178 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>;
1179 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1180 <&topckgen CLK_TOP_MUX_SPI>,
1181 <&infracfg CLK_INFRA_SPI0>;
1182 clock-names = "parent-clk", "sel-clk", "spi-clk";
1183 status = "disabled";
1184 };
1185
1186 svs: svs@1100b000 {
1187 compatible = "mediatek,mt8183-svs";
1188 reg = <0 0x1100b000 0 0x1000>;
1189 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
1190 clocks = <&infracfg CLK_INFRA_THERM>;
1191 clock-names = "main";
1192 nvmem-cells = <&svs_calibration>,
1193 <&thermal_calibration>;
1194 nvmem-cell-names = "svs-calibration-data",
1195 "t-calibration-data";
1196 };
1197
1198 thermal: thermal@1100b000 {
1199 #thermal-sensor-cells = <1>;
1200 compatible = "mediatek,mt8183-thermal";
1201 reg = <0 0x1100b000 0 0x1000>;
1202 clocks = <&infracfg CLK_INFRA_THERM>,
1203 <&infracfg CLK_INFRA_AUXADC>;
1204 clock-names = "therm", "auxadc";
1205 resets = <&infracfg MT8183_INFRACFG_AO_THERM_SW_RST>;
1206 interrupts = <0 76 IRQ_TYPE_LEVEL_LOW>;
1207 mediatek,auxadc = <&auxadc>;
1208 mediatek,apmixedsys = <&apmixedsys>;
1209 nvmem-cells = <&thermal_calibration>;
1210 nvmem-cell-names = "calibration-data";
1211 };
1212
1213 pwm0: pwm@1100e000 {
1214 compatible = "mediatek,mt8183-disp-pwm";
1215 reg = <0 0x1100e000 0 0x1000>;
1216 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
1217 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1218 #pwm-cells = <2>;
1219 clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>,
1220 <&infracfg CLK_INFRA_DISP_PWM>;
1221 clock-names = "main", "mm";
1222 };
1223
1224 pwm1: pwm@11006000 {
1225 compatible = "mediatek,mt8183-pwm";
1226 reg = <0 0x11006000 0 0x1000>;
1227 #pwm-cells = <2>;
1228 clocks = <&infracfg CLK_INFRA_PWM>,
1229 <&infracfg CLK_INFRA_PWM_HCLK>,
1230 <&infracfg CLK_INFRA_PWM1>,
1231 <&infracfg CLK_INFRA_PWM2>,
1232 <&infracfg CLK_INFRA_PWM3>,
1233 <&infracfg CLK_INFRA_PWM4>;
1234 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
1235 "pwm4";
1236 };
1237
1238 i2c3: i2c@1100f000 {
1239 compatible = "mediatek,mt8183-i2c";
1240 reg = <0 0x1100f000 0 0x1000>,
1241 <0 0x11000400 0 0x80>;
1242 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
1243 clocks = <&infracfg CLK_INFRA_I2C3>,
1244 <&infracfg CLK_INFRA_AP_DMA>;
1245 clock-names = "main", "dma";
1246 clock-div = <1>;
1247 #address-cells = <1>;
1248 #size-cells = <0>;
1249 status = "disabled";
1250 };
1251
1252 spi1: spi@11010000 {
1253 compatible = "mediatek,mt8183-spi";
1254 #address-cells = <1>;
1255 #size-cells = <0>;
1256 reg = <0 0x11010000 0 0x1000>;
1257 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>;
1258 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1259 <&topckgen CLK_TOP_MUX_SPI>,
1260 <&infracfg CLK_INFRA_SPI1>;
1261 clock-names = "parent-clk", "sel-clk", "spi-clk";
1262 status = "disabled";
1263 };
1264
1265 i2c1: i2c@11011000 {
1266 compatible = "mediatek,mt8183-i2c";
1267 reg = <0 0x11011000 0 0x1000>,
1268 <0 0x11000480 0 0x80>;
1269 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
1270 clocks = <&infracfg CLK_INFRA_I2C4>,
1271 <&infracfg CLK_INFRA_AP_DMA>;
1272 clock-names = "main", "dma";
1273 clock-div = <1>;
1274 #address-cells = <1>;
1275 #size-cells = <0>;
1276 status = "disabled";
1277 };
1278
1279 spi2: spi@11012000 {
1280 compatible = "mediatek,mt8183-spi";
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1283 reg = <0 0x11012000 0 0x1000>;
1284 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
1285 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1286 <&topckgen CLK_TOP_MUX_SPI>,
1287 <&infracfg CLK_INFRA_SPI2>;
1288 clock-names = "parent-clk", "sel-clk", "spi-clk";
1289 status = "disabled";
1290 };
1291
1292 spi3: spi@11013000 {
1293 compatible = "mediatek,mt8183-spi";
1294 #address-cells = <1>;
1295 #size-cells = <0>;
1296 reg = <0 0x11013000 0 0x1000>;
1297 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>;
1298 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1299 <&topckgen CLK_TOP_MUX_SPI>,
1300 <&infracfg CLK_INFRA_SPI3>;
1301 clock-names = "parent-clk", "sel-clk", "spi-clk";
1302 status = "disabled";
1303 };
1304
1305 i2c9: i2c@11014000 {
1306 compatible = "mediatek,mt8183-i2c";
1307 reg = <0 0x11014000 0 0x1000>,
1308 <0 0x11000180 0 0x80>;
1309 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>;
1310 clocks = <&infracfg CLK_INFRA_I2C1_IMM>,
1311 <&infracfg CLK_INFRA_AP_DMA>,
1312 <&infracfg CLK_INFRA_I2C1_ARBITER>;
1313 clock-names = "main", "dma", "arb";
1314 clock-div = <1>;
1315 #address-cells = <1>;
1316 #size-cells = <0>;
1317 status = "disabled";
1318 };
1319
1320 i2c10: i2c@11015000 {
1321 compatible = "mediatek,mt8183-i2c";
1322 reg = <0 0x11015000 0 0x1000>,
1323 <0 0x11000300 0 0x80>;
1324 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
1325 clocks = <&infracfg CLK_INFRA_I2C2_IMM>,
1326 <&infracfg CLK_INFRA_AP_DMA>,
1327 <&infracfg CLK_INFRA_I2C2_ARBITER>;
1328 clock-names = "main", "dma", "arb";
1329 clock-div = <1>;
1330 #address-cells = <1>;
1331 #size-cells = <0>;
1332 status = "disabled";
1333 };
1334
1335 i2c5: i2c@11016000 {
1336 compatible = "mediatek,mt8183-i2c";
1337 reg = <0 0x11016000 0 0x1000>,
1338 <0 0x11000500 0 0x80>;
1339 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
1340 clocks = <&infracfg CLK_INFRA_I2C5>,
1341 <&infracfg CLK_INFRA_AP_DMA>,
1342 <&infracfg CLK_INFRA_I2C5_ARBITER>;
1343 clock-names = "main", "dma", "arb";
1344 clock-div = <1>;
1345 #address-cells = <1>;
1346 #size-cells = <0>;
1347 status = "disabled";
1348 };
1349
1350 i2c11: i2c@11017000 {
1351 compatible = "mediatek,mt8183-i2c";
1352 reg = <0 0x11017000 0 0x1000>,
1353 <0 0x11000580 0 0x80>;
1354 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>;
1355 clocks = <&infracfg CLK_INFRA_I2C5_IMM>,
1356 <&infracfg CLK_INFRA_AP_DMA>,
1357 <&infracfg CLK_INFRA_I2C5_ARBITER>;
1358 clock-names = "main", "dma", "arb";
1359 clock-div = <1>;
1360 #address-cells = <1>;
1361 #size-cells = <0>;
1362 status = "disabled";
1363 };
1364
1365 spi4: spi@11018000 {
1366 compatible = "mediatek,mt8183-spi";
1367 #address-cells = <1>;
1368 #size-cells = <0>;
1369 reg = <0 0x11018000 0 0x1000>;
1370 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>;
1371 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1372 <&topckgen CLK_TOP_MUX_SPI>,
1373 <&infracfg CLK_INFRA_SPI4>;
1374 clock-names = "parent-clk", "sel-clk", "spi-clk";
1375 status = "disabled";
1376 };
1377
1378 spi5: spi@11019000 {
1379 compatible = "mediatek,mt8183-spi";
1380 #address-cells = <1>;
1381 #size-cells = <0>;
1382 reg = <0 0x11019000 0 0x1000>;
1383 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
1384 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1385 <&topckgen CLK_TOP_MUX_SPI>,
1386 <&infracfg CLK_INFRA_SPI5>;
1387 clock-names = "parent-clk", "sel-clk", "spi-clk";
1388 status = "disabled";
1389 };
1390
1391 i2c7: i2c@1101a000 {
1392 compatible = "mediatek,mt8183-i2c";
1393 reg = <0 0x1101a000 0 0x1000>,
1394 <0 0x11000680 0 0x80>;
1395 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
1396 clocks = <&infracfg CLK_INFRA_I2C7>,
1397 <&infracfg CLK_INFRA_AP_DMA>;
1398 clock-names = "main", "dma";
1399 clock-div = <1>;
1400 #address-cells = <1>;
1401 #size-cells = <0>;
1402 status = "disabled";
1403 };
1404
1405 i2c8: i2c@1101b000 {
1406 compatible = "mediatek,mt8183-i2c";
1407 reg = <0 0x1101b000 0 0x1000>,
1408 <0 0x11000700 0 0x80>;
1409 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
1410 clocks = <&infracfg CLK_INFRA_I2C8>,
1411 <&infracfg CLK_INFRA_AP_DMA>;
1412 clock-names = "main", "dma";
1413 clock-div = <1>;
1414 #address-cells = <1>;
1415 #size-cells = <0>;
1416 status = "disabled";
1417 };
1418
1419 ssusb: usb@11201000 {
1420 compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3";
1421 reg = <0 0x11201000 0 0x2e00>,
1422 <0 0x11203e00 0 0x0100>;
1423 reg-names = "mac", "ippc";
1424 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
1425 phys = <&u2port0 PHY_TYPE_USB2>,
1426 <&u3port0 PHY_TYPE_USB3>;
1427 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
1428 <&infracfg CLK_INFRA_USB>;
1429 clock-names = "sys_ck", "ref_ck";
1430 mediatek,syscon-wakeup = <&pericfg 0x420 101>;
1431 #address-cells = <2>;
1432 #size-cells = <2>;
1433 ranges;
1434 status = "disabled";
1435
1436 usb_host: usb@11200000 {
1437 compatible = "mediatek,mt8183-xhci",
1438 "mediatek,mtk-xhci";
1439 reg = <0 0x11200000 0 0x1000>;
1440 reg-names = "mac";
1441 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
1442 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
1443 <&infracfg CLK_INFRA_USB>;
1444 clock-names = "sys_ck", "ref_ck";
1445 status = "disabled";
1446 };
1447 };
1448
1449 audiosys: audio-controller@11220000 {
1450 compatible = "mediatek,mt8183-audiosys", "syscon";
1451 reg = <0 0x11220000 0 0x1000>;
1452 #clock-cells = <1>;
1453 afe: mt8183-afe-pcm {
1454 compatible = "mediatek,mt8183-audio";
1455 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
1456 resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>;
1457 reset-names = "audiosys";
1458 power-domains =
1459 <&spm MT8183_POWER_DOMAIN_AUDIO>;
1460 clocks = <&audiosys CLK_AUDIO_AFE>,
1461 <&audiosys CLK_AUDIO_DAC>,
1462 <&audiosys CLK_AUDIO_DAC_PREDIS>,
1463 <&audiosys CLK_AUDIO_ADC>,
1464 <&audiosys CLK_AUDIO_PDN_ADDA6_ADC>,
1465 <&audiosys CLK_AUDIO_22M>,
1466 <&audiosys CLK_AUDIO_24M>,
1467 <&audiosys CLK_AUDIO_APLL_TUNER>,
1468 <&audiosys CLK_AUDIO_APLL2_TUNER>,
1469 <&audiosys CLK_AUDIO_I2S1>,
1470 <&audiosys CLK_AUDIO_I2S2>,
1471 <&audiosys CLK_AUDIO_I2S3>,
1472 <&audiosys CLK_AUDIO_I2S4>,
1473 <&audiosys CLK_AUDIO_TDM>,
1474 <&audiosys CLK_AUDIO_TML>,
1475 <&infracfg CLK_INFRA_AUDIO>,
1476 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>,
1477 <&topckgen CLK_TOP_MUX_AUDIO>,
1478 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
1479 <&topckgen CLK_TOP_SYSPLL_D2_D4>,
1480 <&topckgen CLK_TOP_MUX_AUD_1>,
1481 <&topckgen CLK_TOP_APLL1_CK>,
1482 <&topckgen CLK_TOP_MUX_AUD_2>,
1483 <&topckgen CLK_TOP_APLL2_CK>,
1484 <&topckgen CLK_TOP_MUX_AUD_ENG1>,
1485 <&topckgen CLK_TOP_APLL1_D8>,
1486 <&topckgen CLK_TOP_MUX_AUD_ENG2>,
1487 <&topckgen CLK_TOP_APLL2_D8>,
1488 <&topckgen CLK_TOP_MUX_APLL_I2S0>,
1489 <&topckgen CLK_TOP_MUX_APLL_I2S1>,
1490 <&topckgen CLK_TOP_MUX_APLL_I2S2>,
1491 <&topckgen CLK_TOP_MUX_APLL_I2S3>,
1492 <&topckgen CLK_TOP_MUX_APLL_I2S4>,
1493 <&topckgen CLK_TOP_MUX_APLL_I2S5>,
1494 <&topckgen CLK_TOP_APLL12_DIV0>,
1495 <&topckgen CLK_TOP_APLL12_DIV1>,
1496 <&topckgen CLK_TOP_APLL12_DIV2>,
1497 <&topckgen CLK_TOP_APLL12_DIV3>,
1498 <&topckgen CLK_TOP_APLL12_DIV4>,
1499 <&topckgen CLK_TOP_APLL12_DIVB>,
1500 /*<&topckgen CLK_TOP_APLL12_DIV5>,*/
1501 <&clk26m>;
1502 clock-names = "aud_afe_clk",
1503 "aud_dac_clk",
1504 "aud_dac_predis_clk",
1505 "aud_adc_clk",
1506 "aud_adc_adda6_clk",
1507 "aud_apll22m_clk",
1508 "aud_apll24m_clk",
1509 "aud_apll1_tuner_clk",
1510 "aud_apll2_tuner_clk",
1511 "aud_i2s1_bclk_sw",
1512 "aud_i2s2_bclk_sw",
1513 "aud_i2s3_bclk_sw",
1514 "aud_i2s4_bclk_sw",
1515 "aud_tdm_clk",
1516 "aud_tml_clk",
1517 "aud_infra_clk",
1518 "mtkaif_26m_clk",
1519 "top_mux_audio",
1520 "top_mux_aud_intbus",
1521 "top_syspll_d2_d4",
1522 "top_mux_aud_1",
1523 "top_apll1_ck",
1524 "top_mux_aud_2",
1525 "top_apll2_ck",
1526 "top_mux_aud_eng1",
1527 "top_apll1_d8",
1528 "top_mux_aud_eng2",
1529 "top_apll2_d8",
1530 "top_i2s0_m_sel",
1531 "top_i2s1_m_sel",
1532 "top_i2s2_m_sel",
1533 "top_i2s3_m_sel",
1534 "top_i2s4_m_sel",
1535 "top_i2s5_m_sel",
1536 "top_apll12_div0",
1537 "top_apll12_div1",
1538 "top_apll12_div2",
1539 "top_apll12_div3",
1540 "top_apll12_div4",
1541 "top_apll12_divb",
1542 /*"top_apll12_div5",*/
1543 "top_clk26m_clk";
1544 };
1545 };
1546
1547 mmc0: mmc@11230000 {
1548 compatible = "mediatek,mt8183-mmc";
1549 reg = <0 0x11230000 0 0x1000>,
1550 <0 0x11f50000 0 0x1000>;
1551 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
1552 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
1553 <&infracfg CLK_INFRA_MSDC0>,
1554 <&infracfg CLK_INFRA_MSDC0_SCK>;
1555 clock-names = "source", "hclk", "source_cg";
1556 status = "disabled";
1557 };
1558
1559 mmc1: mmc@11240000 {
1560 compatible = "mediatek,mt8183-mmc";
1561 reg = <0 0x11240000 0 0x1000>,
1562 <0 0x11e10000 0 0x1000>;
1563 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
1564 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>,
1565 <&infracfg CLK_INFRA_MSDC1>,
1566 <&infracfg CLK_INFRA_MSDC1_SCK>;
1567 clock-names = "source", "hclk", "source_cg";
1568 status = "disabled";
1569 };
1570
1571 mipi_tx0: dsi-phy@11e50000 {
1572 compatible = "mediatek,mt8183-mipi-tx";
1573 reg = <0 0x11e50000 0 0x1000>;
1574 clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>;
1575 #clock-cells = <0>;
1576 #phy-cells = <0>;
1577 clock-output-names = "mipi_tx0_pll";
1578 nvmem-cells = <&mipi_tx_calibration>;
1579 nvmem-cell-names = "calibration-data";
1580 };
1581
1582 efuse: efuse@11f10000 {
1583 compatible = "mediatek,mt8183-efuse",
1584 "mediatek,efuse";
1585 reg = <0 0x11f10000 0 0x1000>;
1586 #address-cells = <1>;
1587 #size-cells = <1>;
1588 thermal_calibration: calib@180 {
1589 reg = <0x180 0xc>;
1590 };
1591
1592 mipi_tx_calibration: calib@190 {
1593 reg = <0x190 0xc>;
1594 };
1595
1596 svs_calibration: calib@580 {
1597 reg = <0x580 0x64>;
1598 };
1599 };
1600
1601 u3phy: t-phy@11f40000 {
1602 compatible = "mediatek,mt8183-tphy",
1603 "mediatek,generic-tphy-v2";
1604 #address-cells = <1>;
1605 #size-cells = <1>;
1606 ranges = <0 0 0x11f40000 0x1000>;
1607 status = "okay";
1608
1609 u2port0: usb-phy@0 {
1610 reg = <0x0 0x700>;
1611 clocks = <&clk26m>;
1612 clock-names = "ref";
1613 #phy-cells = <1>;
1614 mediatek,discth = <15>;
1615 status = "okay";
1616 };
1617
1618 u3port0: usb-phy@700 {
1619 reg = <0x0700 0x900>;
1620 clocks = <&clk26m>;
1621 clock-names = "ref";
1622 #phy-cells = <1>;
1623 status = "okay";
1624 };
1625 };
1626
1627 mfgcfg: syscon@13000000 {
1628 compatible = "mediatek,mt8183-mfgcfg", "syscon";
1629 reg = <0 0x13000000 0 0x1000>;
1630 #clock-cells = <1>;
1631 };
1632
1633 gpu: gpu@13040000 {
1634 compatible = "mediatek,mt8183b-mali", "arm,mali-bifrost";
1635 reg = <0 0x13040000 0 0x4000>;
1636 interrupts =
1637 <GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>,
1638 <GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>,
1639 <GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>;
1640 interrupt-names = "job", "mmu", "gpu";
1641
1642 clocks = <&mfgcfg CLK_MFG_BG3D>;
1643
1644 power-domains =
1645 <&spm MT8183_POWER_DOMAIN_MFG_CORE0>,
1646 <&spm MT8183_POWER_DOMAIN_MFG_CORE1>,
1647 <&spm MT8183_POWER_DOMAIN_MFG_2D>;
1648 power-domain-names = "core0", "core1", "core2";
1649
1650 operating-points-v2 = <&gpu_opp_table>;
1651 };
1652
1653 mmsys: syscon@14000000 {
1654 compatible = "mediatek,mt8183-mmsys", "syscon";
1655 reg = <0 0x14000000 0 0x1000>;
1656 #clock-cells = <1>;
1657 #reset-cells = <1>;
1658 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1659 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1660 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1661 };
1662
1663 mdp3-rdma0@14001000 {
1664 compatible = "mediatek,mt8183-mdp3-rdma";
1665 reg = <0 0x14001000 0 0x1000>;
1666 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
1667 mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
1668 <CMDQ_EVENT_MDP_RDMA0_EOF>;
1669 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1670 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
1671 <&mmsys CLK_MM_MDP_RSZ1>;
1672 iommus = <&iommu M4U_PORT_MDP_RDMA0>;
1673 mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
1674 <&gce 21 CMDQ_THR_PRIO_LOWEST 0>;
1675 };
1676
1677 mdp3-rsz0@14003000 {
1678 compatible = "mediatek,mt8183-mdp3-rsz";
1679 reg = <0 0x14003000 0 0x1000>;
1680 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
1681 mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>,
1682 <CMDQ_EVENT_MDP_RSZ0_EOF>;
1683 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
1684 };
1685
1686 mdp3-rsz1@14004000 {
1687 compatible = "mediatek,mt8183-mdp3-rsz";
1688 reg = <0 0x14004000 0 0x1000>;
1689 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
1690 mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>,
1691 <CMDQ_EVENT_MDP_RSZ1_EOF>;
1692 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
1693 };
1694
1695 mdp3-wrot0@14005000 {
1696 compatible = "mediatek,mt8183-mdp3-wrot";
1697 reg = <0 0x14005000 0 0x1000>;
1698 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1699 mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
1700 <CMDQ_EVENT_MDP_WROT0_EOF>;
1701 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1702 clocks = <&mmsys CLK_MM_MDP_WROT0>;
1703 iommus = <&iommu M4U_PORT_MDP_WROT0>;
1704 };
1705
1706 mdp3-wdma@14006000 {
1707 compatible = "mediatek,mt8183-mdp3-wdma";
1708 reg = <0 0x14006000 0 0x1000>;
1709 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1710 mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>,
1711 <CMDQ_EVENT_MDP_WDMA0_EOF>;
1712 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1713 clocks = <&mmsys CLK_MM_MDP_WDMA0>;
1714 iommus = <&iommu M4U_PORT_MDP_WDMA0>;
1715 };
1716
1717 ovl0: ovl@14008000 {
1718 compatible = "mediatek,mt8183-disp-ovl";
1719 reg = <0 0x14008000 0 0x1000>;
1720 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
1721 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1722 clocks = <&mmsys CLK_MM_DISP_OVL0>;
1723 iommus = <&iommu M4U_PORT_DISP_OVL0>;
1724 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
1725 };
1726
1727 ovl_2l0: ovl@14009000 {
1728 compatible = "mediatek,mt8183-disp-ovl-2l";
1729 reg = <0 0x14009000 0 0x1000>;
1730 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
1731 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1732 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
1733 iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
1734 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
1735 };
1736
1737 ovl_2l1: ovl@1400a000 {
1738 compatible = "mediatek,mt8183-disp-ovl-2l";
1739 reg = <0 0x1400a000 0 0x1000>;
1740 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
1741 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1742 clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
1743 iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>;
1744 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
1745 };
1746
1747 rdma0: rdma@1400b000 {
1748 compatible = "mediatek,mt8183-disp-rdma";
1749 reg = <0 0x1400b000 0 0x1000>;
1750 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
1751 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1752 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1753 iommus = <&iommu M4U_PORT_DISP_RDMA0>;
1754 mediatek,rdma-fifo-size = <5120>;
1755 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1756 };
1757
1758 rdma1: rdma@1400c000 {
1759 compatible = "mediatek,mt8183-disp-rdma";
1760 reg = <0 0x1400c000 0 0x1000>;
1761 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
1762 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1763 clocks = <&mmsys CLK_MM_DISP_RDMA1>;
1764 iommus = <&iommu M4U_PORT_DISP_RDMA1>;
1765 mediatek,rdma-fifo-size = <2048>;
1766 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1767 };
1768
1769 color0: color@1400e000 {
1770 compatible = "mediatek,mt8183-disp-color",
1771 "mediatek,mt8173-disp-color";
1772 reg = <0 0x1400e000 0 0x1000>;
1773 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
1774 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1775 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1776 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1777 };
1778
1779 ccorr0: ccorr@1400f000 {
1780 compatible = "mediatek,mt8183-disp-ccorr";
1781 reg = <0 0x1400f000 0 0x1000>;
1782 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
1783 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1784 clocks = <&mmsys CLK_MM_DISP_CCORR0>;
1785 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1786 };
1787
1788 aal0: aal@14010000 {
1789 compatible = "mediatek,mt8183-disp-aal";
1790 reg = <0 0x14010000 0 0x1000>;
1791 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
1792 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1793 clocks = <&mmsys CLK_MM_DISP_AAL0>;
1794 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1795 };
1796
1797 gamma0: gamma@14011000 {
1798 compatible = "mediatek,mt8183-disp-gamma";
1799 reg = <0 0x14011000 0 0x1000>;
1800 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
1801 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1802 clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
1803 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1804 };
1805
1806 dither0: dither@14012000 {
1807 compatible = "mediatek,mt8183-disp-dither";
1808 reg = <0 0x14012000 0 0x1000>;
1809 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
1810 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1811 clocks = <&mmsys CLK_MM_DISP_DITHER0>;
1812 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1813 };
1814
1815 dsi0: dsi@14014000 {
1816 compatible = "mediatek,mt8183-dsi";
1817 reg = <0 0x14014000 0 0x1000>;
1818 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
1819 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1820 clocks = <&mmsys CLK_MM_DSI0_MM>,
1821 <&mmsys CLK_MM_DSI0_IF>,
1822 <&mipi_tx0>;
1823 clock-names = "engine", "digital", "hs";
1824 resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
1825 phys = <&mipi_tx0>;
1826 phy-names = "dphy";
1827 };
1828
1829 mutex: mutex@14016000 {
1830 compatible = "mediatek,mt8183-disp-mutex";
1831 reg = <0 0x14016000 0 0x1000>;
1832 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
1833 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1834 mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
1835 <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
1836 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1837 };
1838
1839 larb0: larb@14017000 {
1840 compatible = "mediatek,mt8183-smi-larb";
1841 reg = <0 0x14017000 0 0x1000>;
1842 mediatek,smi = <&smi_common>;
1843 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1844 <&mmsys CLK_MM_SMI_LARB0>;
1845 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1846 clock-names = "apb", "smi";
1847 };
1848
1849 smi_common: smi@14019000 {
1850 compatible = "mediatek,mt8183-smi-common";
1851 reg = <0 0x14019000 0 0x1000>;
1852 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1853 <&mmsys CLK_MM_SMI_COMMON>,
1854 <&mmsys CLK_MM_GALS_COMM0>,
1855 <&mmsys CLK_MM_GALS_COMM1>;
1856 clock-names = "apb", "smi", "gals0", "gals1";
1857 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1858 };
1859
1860 mdp3-ccorr@1401c000 {
1861 compatible = "mediatek,mt8183-mdp3-ccorr";
1862 reg = <0 0x1401c000 0 0x1000>;
1863 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
1864 mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>,
1865 <CMDQ_EVENT_MDP_CCORR_EOF>;
1866 clocks = <&mmsys CLK_MM_MDP_CCORR>;
1867 };
1868
1869 imgsys: syscon@15020000 {
1870 compatible = "mediatek,mt8183-imgsys", "syscon";
1871 reg = <0 0x15020000 0 0x1000>;
1872 #clock-cells = <1>;
1873 };
1874
1875 larb5: larb@15021000 {
1876 compatible = "mediatek,mt8183-smi-larb";
1877 reg = <0 0x15021000 0 0x1000>;
1878 mediatek,smi = <&smi_common>;
1879 clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>,
1880 <&mmsys CLK_MM_GALS_IMG2MM>;
1881 clock-names = "apb", "smi", "gals";
1882 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
1883 };
1884
1885 larb2: larb@1502f000 {
1886 compatible = "mediatek,mt8183-smi-larb";
1887 reg = <0 0x1502f000 0 0x1000>;
1888 mediatek,smi = <&smi_common>;
1889 clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>,
1890 <&mmsys CLK_MM_GALS_IPU2MM>;
1891 clock-names = "apb", "smi", "gals";
1892 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
1893 };
1894
1895 vdecsys: syscon@16000000 {
1896 compatible = "mediatek,mt8183-vdecsys", "syscon";
1897 reg = <0 0x16000000 0 0x1000>;
1898 #clock-cells = <1>;
1899 };
1900
1901 larb1: larb@16010000 {
1902 compatible = "mediatek,mt8183-smi-larb";
1903 reg = <0 0x16010000 0 0x1000>;
1904 mediatek,smi = <&smi_common>;
1905 clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>;
1906 clock-names = "apb", "smi";
1907 power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>;
1908 };
1909
1910 vencsys: syscon@17000000 {
1911 compatible = "mediatek,mt8183-vencsys", "syscon";
1912 reg = <0 0x17000000 0 0x1000>;
1913 #clock-cells = <1>;
1914 };
1915
1916 larb4: larb@17010000 {
1917 compatible = "mediatek,mt8183-smi-larb";
1918 reg = <0 0x17010000 0 0x1000>;
1919 mediatek,smi = <&smi_common>;
1920 clocks = <&vencsys CLK_VENC_LARB>,
1921 <&vencsys CLK_VENC_LARB>;
1922 clock-names = "apb", "smi";
1923 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
1924 };
1925
1926 venc_jpg: venc_jpg@17030000 {
1927 compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc";
1928 reg = <0 0x17030000 0 0x1000>;
1929 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>;
1930 iommus = <&iommu M4U_PORT_JPGENC_RDMA>,
1931 <&iommu M4U_PORT_JPGENC_BSDMA>;
1932 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
1933 clocks = <&vencsys CLK_VENC_JPGENC>;
1934 clock-names = "jpgenc";
1935 };
1936
1937 ipu_conn: syscon@19000000 {
1938 compatible = "mediatek,mt8183-ipu_conn", "syscon";
1939 reg = <0 0x19000000 0 0x1000>;
1940 #clock-cells = <1>;
1941 };
1942
1943 ipu_adl: syscon@19010000 {
1944 compatible = "mediatek,mt8183-ipu_adl", "syscon";
1945 reg = <0 0x19010000 0 0x1000>;
1946 #clock-cells = <1>;
1947 };
1948
1949 ipu_core0: syscon@19180000 {
1950 compatible = "mediatek,mt8183-ipu_core0", "syscon";
1951 reg = <0 0x19180000 0 0x1000>;
1952 #clock-cells = <1>;
1953 };
1954
1955 ipu_core1: syscon@19280000 {
1956 compatible = "mediatek,mt8183-ipu_core1", "syscon";
1957 reg = <0 0x19280000 0 0x1000>;
1958 #clock-cells = <1>;
1959 };
1960
1961 camsys: syscon@1a000000 {
1962 compatible = "mediatek,mt8183-camsys", "syscon";
1963 reg = <0 0x1a000000 0 0x1000>;
1964 #clock-cells = <1>;
1965 };
1966
1967 larb6: larb@1a001000 {
1968 compatible = "mediatek,mt8183-smi-larb";
1969 reg = <0 0x1a001000 0 0x1000>;
1970 mediatek,smi = <&smi_common>;
1971 clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>,
1972 <&mmsys CLK_MM_GALS_CAM2MM>;
1973 clock-names = "apb", "smi", "gals";
1974 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
1975 };
1976
1977 larb3: larb@1a002000 {
1978 compatible = "mediatek,mt8183-smi-larb";
1979 reg = <0 0x1a002000 0 0x1000>;
1980 mediatek,smi = <&smi_common>;
1981 clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>,
1982 <&mmsys CLK_MM_GALS_IPU12MM>;
1983 clock-names = "apb", "smi", "gals";
1984 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
1985 };
1986 };
1987
1988 thermal_zones: thermal-zones {
1989 cpu_thermal: cpu-thermal {
1990 polling-delay-passive = <100>;
1991 polling-delay = <500>;
1992 thermal-sensors = <&thermal 0>;
1993 sustainable-power = <5000>;
1994
1995 trips {
1996 threshold: trip-point0 {
1997 temperature = <68000>;
1998 hysteresis = <2000>;
1999 type = "passive";
2000 };
2001
2002 target: trip-point1 {
2003 temperature = <80000>;
2004 hysteresis = <2000>;
2005 type = "passive";
2006 };
2007
2008 cpu_crit: cpu-crit {
2009 temperature = <115000>;
2010 hysteresis = <2000>;
2011 type = "critical";
2012 };
2013 };
2014
2015 cooling-maps {
2016 map0 {
2017 trip = <&target>;
2018 cooling-device = <&cpu0
2019 THERMAL_NO_LIMIT
2020 THERMAL_NO_LIMIT>,
2021 <&cpu1
2022 THERMAL_NO_LIMIT
2023 THERMAL_NO_LIMIT>,
2024 <&cpu2
2025 THERMAL_NO_LIMIT
2026 THERMAL_NO_LIMIT>,
2027 <&cpu3
2028 THERMAL_NO_LIMIT
2029 THERMAL_NO_LIMIT>;
2030 contribution = <3072>;
2031 };
2032 map1 {
2033 trip = <&target>;
2034 cooling-device = <&cpu4
2035 THERMAL_NO_LIMIT
2036 THERMAL_NO_LIMIT>,
2037 <&cpu5
2038 THERMAL_NO_LIMIT
2039 THERMAL_NO_LIMIT>,
2040 <&cpu6
2041 THERMAL_NO_LIMIT
2042 THERMAL_NO_LIMIT>,
2043 <&cpu7
2044 THERMAL_NO_LIMIT
2045 THERMAL_NO_LIMIT>;
2046 contribution = <1024>;
2047 };
2048 };
2049 };
2050
2051 /* The tzts1 ~ tzts6 don't need to polling */
2052 /* The tzts1 ~ tzts6 don't need to thermal throttle */
2053
2054 tzts1: tzts1 {
2055 polling-delay-passive = <0>;
2056 polling-delay = <0>;
2057 thermal-sensors = <&thermal 1>;
2058 sustainable-power = <5000>;
2059 trips {};
2060 cooling-maps {};
2061 };
2062
2063 tzts2: tzts2 {
2064 polling-delay-passive = <0>;
2065 polling-delay = <0>;
2066 thermal-sensors = <&thermal 2>;
2067 sustainable-power = <5000>;
2068 trips {};
2069 cooling-maps {};
2070 };
2071
2072 tzts3: tzts3 {
2073 polling-delay-passive = <0>;
2074 polling-delay = <0>;
2075 thermal-sensors = <&thermal 3>;
2076 sustainable-power = <5000>;
2077 trips {};
2078 cooling-maps {};
2079 };
2080
2081 tzts4: tzts4 {
2082 polling-delay-passive = <0>;
2083 polling-delay = <0>;
2084 thermal-sensors = <&thermal 4>;
2085 sustainable-power = <5000>;
2086 trips {};
2087 cooling-maps {};
2088 };
2089
2090 tzts5: tzts5 {
2091 polling-delay-passive = <0>;
2092 polling-delay = <0>;
2093 thermal-sensors = <&thermal 5>;
2094 sustainable-power = <5000>;
2095 trips {};
2096 cooling-maps {};
2097 };
2098
2099 tztsABB: tztsABB {
2100 polling-delay-passive = <0>;
2101 polling-delay = <0>;
2102 thermal-sensors = <&thermal 6>;
2103 sustainable-power = <5000>;
2104 trips {};
2105 cooling-maps {};
2106 };
2107 };
2108};