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git01.mediatek.com / filogic / uboot / 53633a893a06bd5a0c807287d9cc29337806eaf7 / . / src / arm64 / freescale / imx93-11x11-evk.dts
blob: 2b9d47716f750ce0ae5857422ecc3c5449128d17 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame^]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2022 NXP
4 */
5
6/dts-v1/;
7
8#include "imx93.dtsi"
9
10/ {
11 model = "NXP i.MX93 11X11 EVK board";
12 compatible = "fsl,imx93-11x11-evk", "fsl,imx93";
13
14 chosen {
15 stdout-path = &lpuart1;
16 };
17
18 reserved-memory {
19 #address-cells = <2>;
20 #size-cells = <2>;
21 ranges;
22
23 linux,cma {
24 compatible = "shared-dma-pool";
25 reusable;
26 alloc-ranges = <0 0x80000000 0 0x40000000>;
27 size = <0 0x10000000>;
28 linux,cma-default;
29 };
30
31 vdev0vring0: vdev0vring0@a4000000 {
32 reg = <0 0xa4000000 0 0x8000>;
33 no-map;
34 };
35
36 vdev0vring1: vdev0vring1@a4008000 {
37 reg = <0 0xa4008000 0 0x8000>;
38 no-map;
39 };
40
41 vdev1vring0: vdev1vring0@a4000000 {
42 reg = <0 0xa4010000 0 0x8000>;
43 no-map;
44 };
45
46 vdev1vring1: vdev1vring1@a4018000 {
47 reg = <0 0xa4018000 0 0x8000>;
48 no-map;
49 };
50
51 rsc_table: rsc-table@2021f000 {
52 reg = <0 0x2021f000 0 0x1000>;
53 no-map;
54 };
55
56 vdevbuffer: vdevbuffer@a4020000 {
57 compatible = "shared-dma-pool";
58 reg = <0 0xa4020000 0 0x100000>;
59 no-map;
60 };
61
62 };
63
64 reg_vref_1v8: regulator-adc-vref {
65 compatible = "regulator-fixed";
66 regulator-name = "vref_1v8";
67 regulator-min-microvolt = <1800000>;
68 regulator-max-microvolt = <1800000>;
69 };
70
71 reg_usdhc2_vmmc: regulator-usdhc2 {
72 compatible = "regulator-fixed";
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
75 regulator-name = "VSD_3V3";
76 regulator-min-microvolt = <3300000>;
77 regulator-max-microvolt = <3300000>;
78 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
79 enable-active-high;
80 };
81};
82
83&adc1 {
84 vref-supply = <&reg_vref_1v8>;
85 status = "okay";
86};
87
88&cm33 {
89 mbox-names = "tx", "rx", "rxdb";
90 mboxes = <&mu1 0 1>,
91 <&mu1 1 1>,
92 <&mu1 3 1>;
93 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
94 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
95 status = "okay";
96};
97
98&mu1 {
99 status = "okay";
100};
101
102&mu2 {
103 status = "okay";
104};
105
106&eqos {
107 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_eqos>;
109 phy-mode = "rgmii-id";
110 phy-handle = <&ethphy1>;
111 status = "okay";
112
113 mdio {
114 compatible = "snps,dwmac-mdio";
115 #address-cells = <1>;
116 #size-cells = <0>;
117 clock-frequency = <5000000>;
118
119 ethphy1: ethernet-phy@1 {
120 reg = <1>;
121 eee-broken-1000t;
122 };
123 };
124};
125
126&fec {
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_fec>;
129 phy-mode = "rgmii-id";
130 phy-handle = <&ethphy2>;
131 fsl,magic-packet;
132 status = "okay";
133
134 mdio {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 clock-frequency = <5000000>;
138
139 ethphy2: ethernet-phy@2 {
140 reg = <2>;
141 eee-broken-1000t;
142 };
143 };
144};
145
146&lpuart1 { /* console */
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_uart1>;
149 status = "okay";
150};
151
152&lpuart5 {
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_uart5>;
155 status = "okay";
156};
157
158&usdhc1 {
159 pinctrl-names = "default", "state_100mhz", "state_200mhz";
160 pinctrl-0 = <&pinctrl_usdhc1>;
161 pinctrl-1 = <&pinctrl_usdhc1>;
162 pinctrl-2 = <&pinctrl_usdhc1>;
163 bus-width = <8>;
164 non-removable;
165 status = "okay";
166};
167
168&usdhc2 {
169 pinctrl-names = "default", "state_100mhz", "state_200mhz";
170 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
171 pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
172 pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
173 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
174 vmmc-supply = <&reg_usdhc2_vmmc>;
175 bus-width = <4>;
176 status = "okay";
177 no-sdio;
178 no-mmc;
179};
180
181&wdog3 {
182 status = "okay";
183};
184
185&iomuxc {
186 pinctrl_eqos: eqosgrp {
187 fsl,pins = <
188 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
189 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
190 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
191 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
192 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
193 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
194 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
195 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
196 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
197 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
198 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
199 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
200 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
201 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
202 >;
203 };
204
205 pinctrl_fec: fecgrp {
206 fsl,pins = <
207 MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
208 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
209 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
210 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
211 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
212 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
213 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
214 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
215 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
216 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
217 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
218 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
219 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
220 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
221 >;
222 };
223
224 pinctrl_uart1: uart1grp {
225 fsl,pins = <
226 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
227 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
228 >;
229 };
230
231 pinctrl_uart5: uart5grp {
232 fsl,pins = <
233 MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
234 MX93_PAD_DAP_TDI__LPUART5_RX 0x31e
235 MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
236 MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
237 >;
238 };
239
240 pinctrl_usdhc1: usdhc1grp {
241 fsl,pins = <
242 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
243 MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
244 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
245 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
246 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
247 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
248 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
249 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
250 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
251 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
252 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
253 >;
254 };
255
256 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
257 fsl,pins = <
258 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
259 >;
260 };
261
262 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
263 fsl,pins = <
264 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
265 >;
266 };
267
268 pinctrl_usdhc2: usdhc2grp {
269 fsl,pins = <
270 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
271 MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe
272 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
273 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
274 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
275 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
276 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
277 >;
278 };
279};