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git01.mediatek.com / filogic / uboot / 53633a893a06bd5a0c807287d9cc29337806eaf7 / . / src / arm64 / freescale / imx8mp-tqma8mpql-mba8mpxl.dts
blob: 4240e20d38ac32eb5fa27d169ddadbe625d4f15f [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2021-2022 TQ-Systems GmbH
4 * Author: Alexander Stein <alexander.stein@tq-group.com>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/leds/common.h>
10#include <dt-bindings/net/ti-dp83867.h>
11#include <dt-bindings/phy/phy-imx8-pcie.h>
12#include <dt-bindings/pwm/pwm.h>
13#include "imx8mp-tqma8mpql.dtsi"
14
15/ {
16 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL";
17 compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
18
19 chosen {
20 stdout-path = &uart4;
21 };
22
23 iio-hwmon {
24 compatible = "iio-hwmon";
25 io-channels = <&adc 0>, <&adc 1>;
26 };
27
28 aliases {
29 mmc0 = &usdhc3;
30 mmc1 = &usdhc2;
31 mmc2 = &usdhc1;
32 rtc0 = &pcf85063;
33 rtc1 = &snvs_rtc;
34 spi0 = &flexspi;
35 spi1 = &ecspi1;
36 spi2 = &ecspi2;
37 spi3 = &ecspi3;
38 };
39
40 backlight_lvds: backlight {
41 compatible = "pwm-backlight";
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_backlight>;
44 pwms = <&pwm2 0 5000000 0>;
45 brightness-levels = <0 4 8 16 32 64 128 255>;
46 default-brightness-level = <7>;
47 power-supply = <&reg_vcc_12v0>;
48 enable-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
49 status = "disabled";
50 };
51
52 clk_xtal25: clk-xtal25 {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <25000000>;
56 };
57
58 fan0: pwm-fan {
59 compatible = "pwm-fan";
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_pwmfan>;
62 fan-supply = <&reg_pwm_fan>;
63 #cooling-cells = <2>;
64 /* typical 25 kHz -> 40.000 nsec */
65 pwms = <&pwm3 0 40000 PWM_POLARITY_INVERTED>;
66 cooling-levels = <0 32 64 128 196 240>;
67 pulses-per-revolution = <2>;
68 interrupt-parent = <&gpio5>;
69 interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
70 status = "disabled";
71 };
72
73 gpio-keys {
74 compatible = "gpio-keys";
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_gpiobutton>;
77 autorepeat;
78
79 switch-1 {
80 label = "S12";
81 linux,code = <BTN_0>;
82 gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
83 wakeup-source;
84 };
85
86 switch-2 {
87 label = "S13";
88 linux,code = <BTN_1>;
89 gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
90 wakeup-source;
91 };
92 };
93
94 gpio-leds {
95 compatible = "gpio-leds";
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_gpioled>;
98
99 led-0 {
100 color = <LED_COLOR_ID_GREEN>;
101 function = LED_FUNCTION_STATUS;
102 function-enumerator = <0>;
103 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
104 linux,default-trigger = "default-on";
105 };
106
107 led-1 {
108 color = <LED_COLOR_ID_GREEN>;
109 function = LED_FUNCTION_HEARTBEAT;
110 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
111 linux,default-trigger = "heartbeat";
112 };
113
114 led-2 {
115 color = <LED_COLOR_ID_YELLOW>;
116 function = LED_FUNCTION_STATUS;
117 function-enumerator = <1>;
118 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
119 };
120 };
121
122 display: display {
123 /*
124 * Display is not fixed, so compatible has to be added from
125 * DT overlay
126 */
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_lvdsdisplay>;
129 power-supply = <&reg_vcc_3v3>;
130 enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
131 backlight = <&backlight_lvds>;
132 status = "disabled";
133 };
134
135 reg_pwm_fan: regulator-pwm-fan {
136 compatible = "regulator-fixed";
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_regpwmfan>;
139 regulator-name = "FAN_PWR";
140 regulator-min-microvolt = <12000000>;
141 regulator-max-microvolt = <12000000>;
142 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
143 enable-active-high;
144 vin-supply = <&reg_vcc_12v0>;
145 };
146
147 reg_usdhc2_vmmc: regulator-usdhc2 {
148 compatible = "regulator-fixed";
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
151 regulator-name = "VSD_3V3";
152 regulator-min-microvolt = <3300000>;
153 regulator-max-microvolt = <3300000>;
154 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
155 enable-active-high;
156 startup-delay-us = <100>;
157 off-on-delay-us = <12000>;
158 };
159
160 reg_vcc_12v0: regulator-12v0 {
161 compatible = "regulator-fixed";
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_reg12v0>;
164 regulator-name = "VCC_12V0";
165 regulator-min-microvolt = <12000000>;
166 regulator-max-microvolt = <12000000>;
167 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
168 enable-active-high;
169 };
170
171 reg_vcc_3v3: regulator-3v3 {
172 compatible = "regulator-fixed";
173 regulator-name = "VCC_3V3";
174 regulator-min-microvolt = <3300000>;
175 regulator-max-microvolt = <3300000>;
176 };
177
178 reg_vcc_5v0: regulator-5v0 {
179 compatible = "regulator-fixed";
180 regulator-name = "VCC_5V0";
181 regulator-min-microvolt = <5000000>;
182 regulator-max-microvolt = <5000000>;
183 };
184
185 reserved-memory {
186 #address-cells = <2>;
187 #size-cells = <2>;
188 ranges;
189
190 ocram: ocram@900000 {
191 no-map;
192 reg = <0 0x900000 0 0x70000>;
193 };
194
195 /* global autoconfigured region for contiguous allocations */
196 linux,cma {
197 compatible = "shared-dma-pool";
198 reusable;
199 size = <0 0x38000000>;
200 alloc-ranges = <0 0x40000000 0 0xB0000000>;
201 linux,cma-default;
202 };
203 };
204
205 sound {
206 compatible = "fsl,imx-audio-tlv320aic32x4";
207 model = "tq-tlv320aic32x";
208 audio-cpu = <&sai3>;
209 audio-codec = <&tlv320aic3x04>;
210 };
211
212 thermal-zones {
213 soc-thermal {
214 trips {
215 soc_active0: trip-active0 {
216 temperature = <40000>;
217 hysteresis = <5000>;
218 type = "active";
219 };
220
221 soc_active1: trip-active1 {
222 temperature = <48000>;
223 hysteresis = <3000>;
224 type = "active";
225 };
226
227 soc_active2: trip-active2 {
228 temperature = <60000>;
229 hysteresis = <10000>;
230 type = "active";
231 };
232 };
233
234 cooling-maps {
235 map1 {
236 trip = <&soc_active0>;
237 cooling-device = <&fan0 1 1>;
238 };
239
240 map2 {
241 trip = <&soc_active1>;
242 cooling-device = <&fan0 2 2>;
243 };
244
245 map3 {
246 trip = <&soc_active2>;
247 cooling-device = <&fan0 3 3>;
248 };
249 };
250 };
251 };
252};
253
254&ecspi1 {
255 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_ecspi1>;
257 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
258 status = "okay";
259};
260
261&ecspi2 {
262 pinctrl-names = "default";
263 pinctrl-0 = <&pinctrl_ecspi2>;
264 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
265 status = "okay";
266};
267
268&ecspi3 {
269 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_ecspi3>;
271 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
272 status = "okay";
273
274 adc: adc@0 {
275 reg = <0>;
276 compatible = "microchip,mcp3202";
277 /* 100 ksps * 18 */
278 spi-max-frequency = <1800000>;
279 vref-supply = <&reg_vcc_3v3>;
280 #io-channel-cells = <1>;
281 };
282};
283
284&eqos {
285 pinctrl-names = "default";
286 pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_eqos_phy>;
287 phy-mode = "rgmii-id";
288 phy-handle = <&ethphy3>;
289 status = "okay";
290
291 mdio {
292 compatible = "snps,dwmac-mdio";
293 #address-cells = <1>;
294 #size-cells = <0>;
295
296 ethphy3: ethernet-phy@3 {
297 compatible = "ethernet-phy-ieee802.3-c22";
298 reg = <3>;
299 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
300 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
301 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
302 ti,dp83867-rxctrl-strap-quirk;
303 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
304 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
305 reset-assert-us = <500000>;
306 reset-deassert-us = <50000>;
307 enet-phy-lane-no-swap;
308 interrupt-parent = <&gpio4>;
309 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
310 };
311 };
312};
313
314&fec {
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_phy>;
317 phy-mode = "rgmii-id";
318 phy-handle = <&ethphy0>;
319 fsl,magic-packet;
320 status = "okay";
321
322 mdio {
323 #address-cells = <1>;
324 #size-cells = <0>;
325
326 ethphy0: ethernet-phy@0 {
327 compatible = "ethernet-phy-ieee802.3-c22";
328 reg = <0>;
329 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
330 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
331 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
332 ti,dp83867-rxctrl-strap-quirk;
333 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
334 reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
335 reset-assert-us = <500000>;
336 reset-deassert-us = <50000>;
337 enet-phy-lane-no-swap;
338 interrupt-parent = <&gpio4>;
339 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
340 };
341 };
342};
343
344&flexcan1 {
345 pinctrl-names = "default";
346 pinctrl-0 = <&pinctrl_flexcan1>;
347 xceiver-supply = <&reg_vcc_3v3>;
348 status = "okay";
349};
350
351&flexcan2 {
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_flexcan2>;
354 xceiver-supply = <&reg_vcc_3v3>;
355 status = "okay";
356};
357
358&gpio1 {
359 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_gpio1>;
361
362 gpio-line-names = "GPO1", "GPO0", "", "GPO3",
363 "", "", "GPO2", "GPI0",
364 "PMIC_IRQ", "GPI1", "OTG_ID", "USB_HUB_RST#",
365 "OTG_PWR", "", "GPI2", "GPI3",
366 "", "", "", "",
367 "", "", "", "",
368 "", "", "", "",
369 "", "", "", "";
370};
371
372&gpio2 {
373 pinctrl-names = "default";
374 pinctrl-0 = <&pinctrl_hoggpio2>;
375
376 gpio-line-names = "", "", "", "",
377 "", "", "VCC12V_EN", "PERST#",
378 "", "", "CLKREQ#", "PEWAKE#",
379 "USDHC2_CD", "", "", "",
380 "", "", "", "V_SD3V3_EN",
381 "", "", "", "",
382 "", "", "", "",
383 "", "", "", "";
384
385 perst-hog {
386 gpio-hog;
387 gpios = <7 0>;
388 output-high;
389 line-name = "PERST#";
390 };
391
392 clkreq-hog {
393 gpio-hog;
394 gpios = <10 0>;
395 input;
396 line-name = "CLKREQ#";
397 };
398
399 pewake-hog {
400 gpio-hog;
401 gpios = <11 0>;
402 input;
403 line-name = "PEWAKE#";
404 };
405};
406
407&gpio3 {
408 gpio-line-names = "", "", "", "",
409 "", "", "", "",
410 "", "", "", "",
411 "", "", "LVDS0_RESET#", "",
412 "", "", "", "LVDS0_BLT_EN",
413 "LVDS0_PWR_EN", "", "", "",
414 "", "", "", "",
415 "", "", "", "";
416};
417
418&gpio4 {
419 pinctrl-names = "default";
420 pinctrl-0 = <&pinctrl_gpio4>;
421
422 gpio-line-names = "ENET0_RST#", "ENET0_INT#", "ENET1_RST#", "ENET1_INT#",
423 "", "", "", "",
424 "", "", "", "",
425 "", "", "", "",
426 "", "", "DP_IRQ", "DSI_EN",
427 "HDMI_OC#", "TEMP_EVENT#", "PCIE_REFCLK_OE#", "",
428 "", "", "", "FAN_PWR",
429 "RTC_EVENT#", "CODEC_RST#", "", "";
430
431 pcie-refclkreq-hog {
432 gpio-hog;
433 gpios = <22 0>;
434 output-high;
435 line-name = "PCIE_REFCLK_OE#";
436 };
437};
438
439&gpio5 {
440 gpio-line-names = "", "", "", "LED2",
441 "LED1", "LED0", "CSI0_RESET#", "CSI0_SYNC",
442 "CSI0_TRIGGER", "CSI0_ENABLE", "", "",
443 "", "ECSPI2_SS0", "", "",
444 "", "", "", "",
445 "", "", "", "",
446 "", "ECSPI3_SS0", "SWITCH_A", "SWITCH_B",
447 "", "", "", "";
448};
449
450&i2c2 {
451 clock-frequency = <384000>;
452 pinctrl-names = "default", "gpio";
453 pinctrl-0 = <&pinctrl_i2c2>;
454 pinctrl-1 = <&pinctrl_i2c2_gpio>;
455 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
456 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
457 status = "okay";
458
459 tlv320aic3x04: audio-codec@18 {
460 compatible = "ti,tlv320aic32x4";
461 pinctrl-names = "default";
462 pinctrl-0 = <&pinctrl_tlv320aic3x04>;
463 reg = <0x18>;
464 clock-names = "mclk";
465 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
466 reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>;
467 iov-supply = <&reg_vcc_3v3>;
468 ldoin-supply = <&reg_vcc_3v3>;
469 };
470
471 se97_1c: temperature-sensor@1c {
472 compatible = "nxp,se97b", "jedec,jc-42.4-temp";
473 reg = <0x1c>;
474 };
475
476 at24c02_54: eeprom@54 {
477 compatible = "nxp,se97b", "atmel,24c02";
478 reg = <0x54>;
479 pagesize = <16>;
480 vcc-supply = <&reg_vcc_3v3>;
481 };
482
483 pcieclk: clock-generator@6a {
484 compatible = "renesas,9fgv0241";
485 reg = <0x6a>;
486 clocks = <&clk_xtal25>;
487 #clock-cells = <1>;
488 };
489};
490
491&i2c4 {
492 clock-frequency = <384000>;
493 pinctrl-names = "default", "gpio";
494 pinctrl-0 = <&pinctrl_i2c4>;
495 pinctrl-1 = <&pinctrl_i2c4_gpio>;
496 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
497 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
498 status = "okay";
499};
500
501&i2c6 {
502 clock-frequency = <384000>;
503 pinctrl-names = "default", "gpio";
504 pinctrl-0 = <&pinctrl_i2c6>;
505 pinctrl-1 = <&pinctrl_i2c6_gpio>;
506 scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
507 sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
508 status = "okay";
509};
510
511&pcf85063 {
512 /* RTC_EVENT# is connected on MBa8MPxL */
513 pinctrl-names = "default";
514 pinctrl-0 = <&pinctrl_pcf85063>;
515 interrupt-parent = <&gpio4>;
516 interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
517};
518
519&pcie_phy {
520 fsl,clkreq-unsupported;
521 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
522 clocks = <&pcieclk 0>;
523 clock-names = "ref";
524 status = "okay";
525};
526
527&pcie {
528 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
529 <&clk IMX8MP_CLK_HSIO_AXI>,
530 <&clk IMX8MP_CLK_PCIE_ROOT>;
531 clock-names = "pcie", "pcie_bus", "pcie_aux";
532 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
533 assigned-clock-rates = <10000000>;
534 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
535 status = "okay";
536};
537
538&pwm2 {
539 pinctrl-names = "default";
540 pinctrl-0 = <&pinctrl_pwm2>;
541 status = "disabled";
542};
543
544&pwm3 {
545 pinctrl-names = "default";
546 pinctrl-0 = <&pinctrl_pwm3>;
547 status = "okay";
548};
549
550&sai3 {
551 pinctrl-names = "default";
552 pinctrl-0 = <&pinctrl_sai3>;
553 assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
554 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
555 assigned-clock-rates = <12288000>;
556 fsl,sai-mclk-direction-output;
557 status = "okay";
558};
559
560&snvs_pwrkey {
561 status = "okay";
562};
563
564&uart1 {
565 pinctrl-names = "default";
566 pinctrl-0 = <&pinctrl_uart1>;
567 assigned-clocks = <&clk IMX8MP_CLK_UART1>;
568 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
569 status = "okay";
570};
571
572&uart2 {
573 pinctrl-names = "default";
574 pinctrl-0 = <&pinctrl_uart2>;
575 assigned-clocks = <&clk IMX8MP_CLK_UART2>;
576 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
577 status = "okay";
578};
579
580&uart3 {
581 pinctrl-names = "default";
582 pinctrl-0 = <&pinctrl_uart3>;
583 assigned-clocks = <&clk IMX8MP_CLK_UART3>;
584 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
585 status = "okay";
586};
587
588&uart4 {
589 /* console */
590 pinctrl-names = "default";
591 pinctrl-0 = <&pinctrl_uart4>;
592 status = "okay";
593};
594
595&usb3_0 {
596 pinctrl-names = "default";
597 pinctrl-0 = <&pinctrl_usb0>;
598 fsl,over-current-active-low;
599 status = "okay";
600};
601
602&usb3_1 {
603 fsl,disable-port-power-control;
604 fsl,permanently-attached;
605 dr_mode = "host";
606 status = "okay";
607};
608
609&usb3_phy0 {
610 vbus-supply = <&reg_vcc_5v0>;
611 status = "okay";
612};
613
614&usb3_phy1 {
615 vbus-supply = <&reg_vcc_5v0>;
616 status = "okay";
617};
618
619&usb_dwc3_0 {
620 /* dual role is implemented, but not a full featured OTG */
621 hnp-disable;
622 srp-disable;
623 adp-disable;
624 dr_mode = "otg";
625 usb-role-switch;
626 role-switch-default-mode = "peripheral";
627 status = "okay";
628
629 connector {
630 compatible = "gpio-usb-b-connector", "usb-b-connector";
631 type = "micro";
632 label = "X29";
633 pinctrl-names = "default";
634 pinctrl-0 = <&pinctrl_usbcon0>;
635 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
636 };
637};
638
639&usb_dwc3_1 {
640 dr_mode = "host";
641 #address-cells = <1>;
642 #size-cells = <0>;
643 pinctrl-names = "default";
644 pinctrl-0 = <&pinctrl_usbhub>;
645 status = "okay";
646
647 hub_2_0: hub@1 {
648 compatible = "usb451,8142";
649 reg = <1>;
650 peer-hub = <&hub_3_0>;
651 reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
652 vdd-supply = <&reg_vcc_3v3>;
653 };
654
655 hub_3_0: hub@2 {
656 compatible = "usb451,8140";
657 reg = <2>;
658 peer-hub = <&hub_2_0>;
659 reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
660 vdd-supply = <&reg_vcc_3v3>;
661 };
662};
663
664&usdhc2 {
665 pinctrl-names = "default", "state_100mhz", "state_200mhz";
666 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
667 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
668 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
669 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
670 vmmc-supply = <&reg_usdhc2_vmmc>;
671 no-mmc;
672 no-sdio;
673 disable-wp;
674 bus-width = <4>;
675 status = "okay";
676};
677
678&iomuxc {
679 pinctrl_backlight: backlightgrp {
680 fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x14>;
681 };
682
683 pinctrl_flexcan1: flexcan1grp {
684 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x150>,
685 <MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x150>;
686 };
687
688 pinctrl_flexcan2: flexcan2grp {
689 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x150>,
690 <MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x150>;
691 };
692
693 /* only on X57, primary used as CSI0 control signals */
694 pinctrl_ecspi1: ecspi1grp {
695 fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c0>,
696 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1c0>,
697 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1c0>,
698 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c0>;
699 };
700
701 /* on X63 and optionally on X57, can also be used as CSI1 control signals */
702 pinctrl_ecspi2: ecspi2grp {
703 fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1c0>,
704 <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1c0>,
705 <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1c0>,
706 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c0>;
707 };
708
709 pinctrl_ecspi3: ecspi3grp {
710 fsl,pins = <MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x1c0>,
711 <MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x1c0>,
712 <MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x1c0>,
713 <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1c0>;
714 };
715
716 pinctrl_eqos: eqosgrp {
717 fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x40000044>,
718 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x40000044>,
719 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>,
720 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>,
721 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>,
722 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>,
723 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>,
724 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>,
725 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12>,
726 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12>,
727 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>,
728 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>,
729 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>,
730 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>;
731 };
732
733 pinctrl_eqos_event: eqosevtgrp {
734 fsl,pins = <MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x100>,
735 <MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1c0>;
736 };
737
738 pinctrl_eqos_phy: eqosphygrp {
739 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x100>,
740 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c0>;
741 };
742
743 pinctrl_fec: fecgrp {
744 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x40000044>,
745 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x40000044>,
746 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>,
747 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>,
748 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>,
749 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>,
750 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>,
751 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>,
752 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12>,
753 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12>,
754 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x12>,
755 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x12>,
756 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x12>,
757 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14>;
758 };
759
760 pinctrl_fec_event: fecevtgrp {
761 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x100>,
762 <MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1c0>;
763 };
764
765 pinctrl_fec_phy: fecphygrp {
766 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x100>,
767 <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x1c0>;
768 };
769
770 pinctrl_fec_phyalt: fecphyaltgrp {
771 fsl,pins = <MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x180>,
772 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x180>;
773 };
774
775 pinctrl_gpiobutton: gpiobuttongrp {
776 fsl,pins = <MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x10>,
777 <MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x10>;
778 };
779
780 pinctrl_gpioled: gpioledgrp {
781 fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x14>,
782 <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x14>,
783 <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x14>;
784 };
785
786 pinctrl_gpio1: gpio1grp {
787 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x10>,
788 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x10>,
789 <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x10>,
790 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10>,
791 <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x80>,
792 <MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x80>,
793 <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x80>,
794 <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x80>;
795 };
796
797 pinctrl_gpio4: gpio4grp {
798 fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x180>,
799 <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x180>;
800 };
801
802 pinctrl_hdmi: hdmigrp {
803 fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>,
804 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>,
805 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>,
806 <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000010>;
807 };
808
809 pinctrl_hoggpio2: hoggpio2grp {
810 fsl,pins = <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x140>,
811 <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x140>,
812 <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140>;
813 };
814
815 pinctrl_i2c2: i2c2grp {
816 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e2>,
817 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e2>;
818 };
819
820 pinctrl_i2c2_gpio: i2c2-gpiogrp {
821 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001e2>,
822 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001e2>;
823 };
824
825 pinctrl_i2c4: i2c4grp {
826 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001e2>,
827 <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001e2>;
828 };
829
830 pinctrl_i2c4_gpio: i2c4-gpiogrp {
831 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001e2>,
832 <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001e2>;
833 };
834
835 pinctrl_i2c6: i2c6grp {
836 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x400001e2>,
837 <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x400001e2>;
838 };
839
840 pinctrl_i2c6_gpio: i2c6-gpiogrp {
841 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x400001e2>,
842 <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x400001e2>;
843 };
844
845 pinctrl_lvdsdisplay: lvdsdisplaygrp {
846 fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x10>; /* Power enable */
847 };
848
849 pinctrl_pcf85063: pcf85063grp {
850 fsl,pins = <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x80>;
851 };
852
853 /* LVDS Backlight */
854 pinctrl_pwm2: pwm2grp {
855 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x14>;
856 };
857
858 /* FAN */
859 pinctrl_pwm3: pwm3grp {
860 fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x14>;
861 };
862
863 pinctrl_pwmfan: pwmfangrp {
864 fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x80>; /* FAN RPM */
865 };
866
867 pinctrl_reg12v0: reg12v0grp {
868 fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140>; /* VCC12V enable */
869 };
870
871 pinctrl_regpwmfan: regpwmfangrp {
872 fsl,pins = <MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x80>;
873 };
874
875 pinctrl_sai3: sai3grp {
876 fsl,pins = <
877 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x94
878 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x94
879 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x94
880 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x94
881 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0x94
882 >;
883 };
884
885 pinctrl_tlv320aic3x04: tlv320aic3x04grp {
886 fsl,pins = <
887 /* CODEC RST# */
888 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x180
889 >;
890 };
891
892 /* X61 */
893 pinctrl_uart1: uart1grp {
894 fsl,pins = <MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x140>,
895 <MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x140>;
896 };
897
898 /* X61 */
899 pinctrl_uart2: uart2grp {
900 fsl,pins = <MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x140>,
901 <MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x140>;
902 };
903
904 pinctrl_uart3: uart3grp {
905 fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140>,
906 <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140>;
907 };
908
909 pinctrl_uart4: uart4grp {
910 fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140>,
911 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140>;
912 };
913
914 pinctrl_usb0: usb0grp {
915 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c0>,
916 <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x1c0>;
917 };
918
919 pinctrl_usbcon0: usb0congrp {
920 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c0>;
921 };
922
923 pinctrl_usbhub: usbhubgrp {
924 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x10>;
925 };
926
927 pinctrl_usdhc2: usdhc2grp {
928 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>,
929 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>,
930 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>,
931 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>,
932 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>,
933 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>,
934 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
935 };
936
937 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
938 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
939 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
940 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
941 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
942 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
943 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
944 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
945 };
946
947 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
948 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
949 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
950 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
951 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
952 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
953 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
954 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
955 };
956
957 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
958 fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0>;
959 };
960};