src/arm64/exynos/exynos7.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung Exynos7 SoC device tree source
 *
 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 */

#include <dt-bindings/clock/exynos7-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "samsung,exynos7";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		pinctrl0 = &pinctrl_alive;
		pinctrl1 = &pinctrl_bus0;
		pinctrl2 = &pinctrl_nfc;
		pinctrl3 = &pinctrl_touch;
		pinctrl4 = &pinctrl_ff;
		pinctrl5 = &pinctrl_ese;
		pinctrl6 = &pinctrl_fsys0;
		pinctrl7 = &pinctrl_fsys1;
		pinctrl8 = &pinctrl_bus1;
	};

	arm-pmu {
		compatible = "arm,cortex-a57-pmu";
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
				     <&cpu_atlas2>, <&cpu_atlas3>;
	};

	fin_pll: clock {
		/* XXTI */
		compatible = "fixed-clock";
		clock-output-names = "fin_pll";
		#clock-cells = <0>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu_atlas0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x0>;
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&atlas_l2>;
		};

		cpu_atlas1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x1>;
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&atlas_l2>;
		};

		cpu_atlas2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x2>;
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&atlas_l2>;
		};

		cpu_atlas3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x3>;
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&atlas_l2>;
		};

		atlas_l2: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0x200000>;
			cache-line-size = <64>;
			cache-sets = <2048>;
		};
	};

	psci {
		compatible = "arm,psci";
		method = "smc";
		cpu_off = <0x84000002>;
		cpu_on = <0xc4000003>;
	};

	soc: soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0x18000000>;

		chipid@10000000 {
			compatible = "samsung,exynos4210-chipid";
			reg = <0x10000000 0x100>;
		};

		gic: interrupt-controller@11001000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x11001000 0x1000>,
			      <0x11002000 0x2000>,
			      <0x11004000 0x2000>,
			      <0x11006000 0x2000>;
		};

		pdma0: dma-controller@10e10000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x10e10000 0x1000>;
			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_fsys0 ACLK_PDMA0>;
			clock-names = "apb_pclk";
			#dma-cells = <1>;
		};

		pdma1: dma-controller@10eb0000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x10eb0000 0x1000>;
			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_fsys0 ACLK_PDMA1>;
			clock-names = "apb_pclk";
			#dma-cells = <1>;
		};

		clock_topc: clock-controller@10570000 {
			compatible = "samsung,exynos7-clock-topc";
			reg = <0x10570000 0x10000>;
			#clock-cells = <1>;
		};

		clock_top0: clock-controller@105d0000 {
			compatible = "samsung,exynos7-clock-top0";
			reg = <0x105d0000 0xb000>;
			#clock-cells = <1>;
			clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
				 <&clock_topc DOUT_SCLK_BUS1_PLL>,
				 <&clock_topc DOUT_SCLK_CC_PLL>,
				 <&clock_topc DOUT_SCLK_MFC_PLL>,
				 <&clock_topc DOUT_SCLK_AUD_PLL>;
			clock-names = "fin_pll", "dout_sclk_bus0_pll",
				      "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
				      "dout_sclk_mfc_pll", "dout_sclk_aud_pll";
		};

		clock_top1: clock-controller@105e0000 {
			compatible = "samsung,exynos7-clock-top1";
			reg = <0x105e0000 0xb000>;
			#clock-cells = <1>;
			clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
				 <&clock_topc DOUT_SCLK_BUS1_PLL>,
				 <&clock_topc DOUT_SCLK_CC_PLL>,
				 <&clock_topc DOUT_SCLK_MFC_PLL>;
			clock-names = "fin_pll", "dout_sclk_bus0_pll",
				      "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
				      "dout_sclk_mfc_pll";
		};

		clock_ccore: clock-controller@105b0000 {
			compatible = "samsung,exynos7-clock-ccore";
			reg = <0x105b0000 0xd00>;
			#clock-cells = <1>;
			clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
			clock-names = "fin_pll", "dout_aclk_ccore_133";
		};

		clock_peric0: clock-controller@13610000 {
			compatible = "samsung,exynos7-clock-peric0";
			reg = <0x13610000 0xd00>;
			#clock-cells = <1>;
			clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
				 <&clock_top0 CLK_SCLK_UART0>;
			clock-names = "fin_pll", "dout_aclk_peric0_66",
				      "sclk_uart0";
		};

		clock_peric1: clock-controller@14c80000 {
			compatible = "samsung,exynos7-clock-peric1";
			reg = <0x14c80000 0xd00>;
			#clock-cells = <1>;
			clocks = <&fin_pll>,
				 <&clock_top0 DOUT_ACLK_PERIC1>,
				 <&clock_top0 CLK_SCLK_UART1>,
				 <&clock_top0 CLK_SCLK_UART2>,
				 <&clock_top0 CLK_SCLK_UART3>,
				 <&clock_top0 CLK_SCLK_SPI0>,
				 <&clock_top0 CLK_SCLK_SPI1>,
				 <&clock_top0 CLK_SCLK_SPI2>,
				 <&clock_top0 CLK_SCLK_SPI3>,
				 <&clock_top0 CLK_SCLK_SPI4>,
				 <&clock_top0 CLK_SCLK_I2S1>,
				 <&clock_top0 CLK_SCLK_PCM1>,
				 <&clock_top0 CLK_SCLK_SPDIF>;
			clock-names = "fin_pll",
				      "dout_aclk_peric1_66",
				      "sclk_uart1",
				      "sclk_uart2",
				      "sclk_uart3",
				      "sclk_spi0",
				      "sclk_spi1",
				      "sclk_spi2",
				      "sclk_spi3",
				      "sclk_spi4",
				      "sclk_i2s1",
				      "sclk_pcm1",
				      "sclk_spdif";
		};

		clock_peris: clock-controller@10040000 {
			compatible = "samsung,exynos7-clock-peris";
			reg = <0x10040000 0xd00>;
			#clock-cells = <1>;
			clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>;
			clock-names = "fin_pll", "dout_aclk_peris_66";
		};

		clock_fsys0: clock-controller@10e90000 {
			compatible = "samsung,exynos7-clock-fsys0";
			reg = <0x10e90000 0xd00>;
			#clock-cells = <1>;
			clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
				 <&clock_top1 DOUT_SCLK_MMC2>;
			clock-names = "fin_pll", "dout_aclk_fsys0_200",
				      "dout_sclk_mmc2";
		};

		clock_fsys1: clock-controller@156e0000 {
			compatible = "samsung,exynos7-clock-fsys1";
			reg = <0x156e0000 0xd00>;
			#clock-cells = <1>;
			clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
				 <&clock_top1 DOUT_SCLK_MMC0>,
				 <&clock_top1 DOUT_SCLK_MMC1>,
				 <&clock_top1 DOUT_SCLK_UFSUNIPRO20>,
				 <&clock_top1 DOUT_SCLK_PHY_FSYS1>,
				 <&clock_top1 DOUT_SCLK_PHY_FSYS1_26M>;
			clock-names = "fin_pll", "dout_aclk_fsys1_200",
				      "dout_sclk_mmc0", "dout_sclk_mmc1",
				      "dout_sclk_ufsunipro20", "dout_sclk_phy_fsys1",
				      "dout_sclk_phy_fsys1_26m";
		};

		serial_0: serial@13630000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x13630000 0x100>;
			interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_peric0 PCLK_UART0>,
				 <&clock_peric0 SCLK_UART0>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		serial_1: serial@14c20000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x14c20000 0x100>;
			interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_peric1 PCLK_UART1>,
				 <&clock_peric1 SCLK_UART1>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		serial_2: serial@14c30000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x14c30000 0x100>;
			interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_peric1 PCLK_UART2>,
				 <&clock_peric1 SCLK_UART2>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		serial_3: serial@14c40000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x14c40000 0x100>;
			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_peric1 PCLK_UART3>,
				 <&clock_peric1 SCLK_UART3>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		pinctrl_alive: pinctrl@10580000 {
			compatible = "samsung,exynos7-pinctrl";
			reg = <0x10580000 0x1000>;

			wakeup-interrupt-controller {
				compatible = "samsung,exynos7-wakeup-eint";
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		pinctrl_bus0: pinctrl@13470000 {
			compatible = "samsung,exynos7-pinctrl";
			reg = <0x13470000 0x1000>;
			interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_nfc: pinctrl@14cd0000 {
			compatible = "samsung,exynos7-pinctrl";
			reg = <0x14cd0000 0x1000>;
			interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_touch: pinctrl@14ce0000 {
			compatible = "samsung,exynos7-pinctrl";
			reg = <0x14ce0000 0x1000>;
			interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_ff: pinctrl@14c90000 {
			compatible = "samsung,exynos7-pinctrl";
			reg = <0x14c90000 0x1000>;
			interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_ese: pinctrl@14ca0000 {
			compatible = "samsung,exynos7-pinctrl";
			reg = <0x14ca0000 0x1000>;
			interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_fsys0: pinctrl@10e60000 {
			compatible = "samsung,exynos7-pinctrl";
			reg = <0x10e60000 0x1000>;
			interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_fsys1: pinctrl@15690000 {
			compatible = "samsung,exynos7-pinctrl";
			reg = <0x15690000 0x1000>;
			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_bus1: pinctrl@14870000 {
			compatible = "samsung,exynos7-pinctrl";
			reg = <0x14870000 0x1000>;
			interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
		};

		hsi2c_0: i2c@13640000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x13640000 0x1000>;
			interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c0_bus>;
			clocks = <&clock_peric0 PCLK_HSI2C0>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		hsi2c_1: i2c@13650000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x13650000 0x1000>;
			interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c1_bus>;
			clocks = <&clock_peric0 PCLK_HSI2C1>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		hsi2c_2: i2c@14e60000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x14e60000 0x1000>;
			interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c2_bus>;
			clocks = <&clock_peric1 PCLK_HSI2C2>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		hsi2c_3: i2c@14e70000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x14e70000 0x1000>;
			interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c3_bus>;
			clocks = <&clock_peric1 PCLK_HSI2C3>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		hsi2c_4: i2c@13660000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x13660000 0x1000>;
			interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c4_bus>;
			clocks = <&clock_peric0 PCLK_HSI2C4>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		hsi2c_5: i2c@13670000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x13670000 0x1000>;
			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c5_bus>;
			clocks = <&clock_peric0 PCLK_HSI2C5>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		hsi2c_6: i2c@14e00000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x14e00000 0x1000>;
			interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c6_bus>;
			clocks = <&clock_peric1 PCLK_HSI2C6>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		hsi2c_7: i2c@13e10000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x13e10000 0x1000>;
			interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c7_bus>;
			clocks = <&clock_peric1 PCLK_HSI2C7>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		hsi2c_8: i2c@14e20000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x14e20000 0x1000>;
			interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c8_bus>;
			clocks = <&clock_peric1 PCLK_HSI2C8>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		hsi2c_9: i2c@13680000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x13680000 0x1000>;
			interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c9_bus>;
			clocks = <&clock_peric0 PCLK_HSI2C9>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		hsi2c_10: i2c@13690000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x13690000 0x1000>;
			interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c10_bus>;
			clocks = <&clock_peric0 PCLK_HSI2C10>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		hsi2c_11: i2c@136a0000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x136a0000 0x1000>;
			interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c11_bus>;
			clocks = <&clock_peric0 PCLK_HSI2C11>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		pmu_system_controller: system-controller@105c0000 {
			compatible = "samsung,exynos7-pmu", "syscon";
			reg = <0x105c0000 0x5000>;
		};

		rtc: rtc@10590000 {
			compatible = "samsung,s3c6410-rtc";
			reg = <0x10590000 0x100>;
			interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_ccore PCLK_RTC>;
			clock-names = "rtc";
			status = "disabled";
		};

		watchdog: watchdog@101d0000 {
			compatible = "samsung,exynos7-wdt";
			reg = <0x101d0000 0x100>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_peris PCLK_WDT>;
			clock-names = "watchdog";
			samsung,syscon-phandle = <&pmu_system_controller>;
			status = "disabled";
		};

		gpu: gpu@14ac0000 {
			compatible = "samsung,exynos5433-mali", "arm,mali-t760";
			reg = <0x14ac0000 0x5000>;
			interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "job", "mmu", "gpu";
			status = "disabled";
			/* TODO: operating points for DVFS, cooling device */
		};

		mmc_0: mmc@15740000 {
			compatible = "samsung,exynos7-dw-mshc-smu";
			interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x15740000 0x2000>;
			clocks = <&clock_fsys1 ACLK_MMC0>,
				 <&clock_top1 CLK_SCLK_MMC0>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x40>;
			status = "disabled";
		};

		mmc_1: mmc@15750000 {
			compatible = "samsung,exynos7-dw-mshc";
			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x15750000 0x2000>;
			clocks = <&clock_fsys1 ACLK_MMC1>,
				 <&clock_top1 CLK_SCLK_MMC1>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x40>;
			status = "disabled";
		};

		mmc_2: mmc@15560000 {
			compatible = "samsung,exynos7-dw-mshc-smu";
			interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x15560000 0x2000>;
			clocks = <&clock_fsys0 ACLK_MMC2>,
				 <&clock_top1 CLK_SCLK_MMC2>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x40>;
			status = "disabled";
		};

		adc: adc@13620000 {
			compatible = "samsung,exynos7-adc";
			reg = <0x13620000 0x100>;
			interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_peric0 PCLK_ADCIF>;
			clock-names = "adc";
			#io-channel-cells = <1>;
			status = "disabled";
		};

		pwm: pwm@136c0000 {
			compatible = "samsung,exynos4210-pwm";
			reg = <0x136c0000 0x100>;
			interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
			samsung,pwm-outputs = <0>, <1>, <2>, <3>;
			#pwm-cells = <3>;
			clocks = <&clock_peric0 PCLK_PWM>;
			clock-names = "timers";
		};

		tmuctrl_0: tmu@10060000 {
			compatible = "samsung,exynos7-tmu";
			reg = <0x10060000 0x200>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_peris PCLK_TMU>,
				 <&clock_peris SCLK_TMU>;
			clock-names = "tmu_apbif", "tmu_sclk";
			#thermal-sensor-cells = <0>;
		};

		ufs: ufs@15570000 {
			compatible = "samsung,exynos7-ufs";
			reg = <0x15570000 0x100>,  /* 0: HCI standard */
				<0x15570100 0x100>,  /* 1: Vendor specificed */
				<0x15571000 0x200>,  /* 2: UNIPRO */
				<0x15572000 0x300>;  /* 3: UFS protector */
			reg-names = "hci", "vs_hci", "unipro", "ufsp";
			interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
				<&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
			clock-names = "core_clk", "sclk_unipro_main";
			freq-table-hz = <0 0>, <0 0>;
			pinctrl-names = "default";
			pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
			phys = <&ufs_phy>;
			phy-names = "ufs-phy";
			status = "disabled";
		};

		ufs_phy: ufs-phy@15571800 {
			compatible = "samsung,exynos7-ufs-phy";
			reg = <0x15571800 0x240>;
			reg-names = "phy-pma";
			samsung,pmu-syscon = <&pmu_system_controller>;
			#phy-cells = <0>;
			clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
				 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
				 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
				 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
			clock-names = "ref_clk", "rx1_symbol_clk",
				      "rx0_symbol_clk",
				      "tx0_symbol_clk";
		};

		usbdrd_phy: phy@15500000 {
			compatible = "samsung,exynos7-usbdrd-phy";
			reg = <0x15500000 0x100>;
			clocks = <&clock_fsys0 ACLK_USBDRD300>,
			       <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>,
			       <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>,
			       <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,
			       <&clock_fsys0 SCLK_USBDRD300_REFCLK>;
			clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp";
			samsung,pmu-syscon = <&pmu_system_controller>;
			#phy-cells = <1>;
		};

		usbdrd: usb@15400000 {
			compatible = "samsung,exynos7-dwusb3";
			clocks = <&clock_fsys0 ACLK_USBDRD300>,
			       <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>,
			       <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>;
			clock-names = "usbdrd30", "usbdrd30_susp_clk",
				"usbdrd30_axius_clk";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x15400000 0x10000>;

			usb@0 {
				compatible = "snps,dwc3";
				reg = <0x0 0x10000>;
				interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
				phy-names = "usb2-phy", "usb3-phy";
			};
		};
	};

	thermal-zones {
		atlas_thermal: cluster0-thermal {
			polling-delay-passive = <0>; /* milliseconds */
			polling-delay = <0>; /* milliseconds */
			thermal-sensors = <&tmuctrl_0>;
			#include "exynos7-trip-points.dtsi"
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13
				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
	};
};

#include "exynos7-pinctrl.dtsi"
#include "arm/samsung/exynos-syscon-restart.dtsi"