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git01.mediatek.com / filogic / uboot / 53633a893a06bd5a0c807287d9cc29337806eaf7 / . / src / arm / nxp / vf / vf610-zii-scu4-aib.dts
blob: df1335492a199841483dc9facd40834fab48003c [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame^]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2//
3// Copyright (C) 2016-2018 Zodiac Inflight Innovations
4
5/dts-v1/;
6#include "vf610.dtsi"
7
8/ {
9 model = "ZII VF610 SCU4 AIB";
10 compatible = "zii,vf610scu4-aib", "zii,vf610dev", "fsl,vf610";
11
12 chosen {
13 stdout-path = &uart0;
14 };
15
16 memory@80000000 {
17 device_type = "memory";
18 reg = <0x80000000 0x20000000>;
19 };
20
21 gpio-leds {
22 compatible = "gpio-leds";
23 pinctrl-0 = <&pinctrl_leds_debug>;
24 pinctrl-names = "default";
25
26 led-debug {
27 label = "zii:green:debug1";
28 gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
29 linux,default-trigger = "heartbeat";
30 };
31 };
32
33 mdio-mux {
34 compatible = "mdio-mux-gpio";
35 pinctrl-0 = <&pinctrl_mdio_mux>;
36 pinctrl-names = "default";
37 gpios = <&gpio4 4 GPIO_ACTIVE_HIGH
38 &gpio4 5 GPIO_ACTIVE_HIGH
39 &gpio3 30 GPIO_ACTIVE_HIGH
40 &gpio3 31 GPIO_ACTIVE_HIGH>;
41 mdio-parent-bus = <&mdio1>;
42 #address-cells = <1>;
43 #size-cells = <0>;
44
45 mdio_mux_1: mdio@1 {
46 reg = <1>;
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 switch0: switch0@0 {
51 compatible = "marvell,mv88e6190";
52 reg = <0>;
53 dsa,member = <0 0>;
54 eeprom-length = <65536>;
55
56 ports {
57 #address-cells = <1>;
58 #size-cells = <0>;
59
60 port@0 {
61 reg = <0>;
62 phy-mode = "rmii";
63 ethernet = <&fec1>;
64
65 fixed-link {
66 speed = <100>;
67 full-duplex;
68 };
69 };
70
71 port@1 {
72 reg = <1>;
73 label = "aib2main_1";
74 };
75
76 port@2 {
77 reg = <2>;
78 label = "aib2main_2";
79 };
80
81 port@3 {
82 reg = <3>;
83 label = "eth_cu_1000_5";
84 };
85
86 port@4 {
87 reg = <4>;
88 label = "eth_cu_1000_6";
89 };
90
91 port@5 {
92 reg = <5>;
93 label = "eth_cu_1000_4";
94 };
95
96 port@6 {
97 reg = <6>;
98 label = "eth_cu_1000_7";
99 };
100
101 port@7 {
102 reg = <7>;
103 label = "modem_pic";
104
105 fixed-link {
106 speed = <100>;
107 full-duplex;
108 };
109 };
110
111 switch0port10: port@10 {
112 reg = <10>;
113 label = "dsa";
114 phy-mode = "xgmii";
115 link = <&switch1port10
116 &switch3port10
117 &switch2port10>;
118
119 fixed-link {
120 speed = <10000>;
121 full-duplex;
122 };
123 };
124 };
125 };
126 };
127
128 mdio_mux_2: mdio@2 {
129 reg = <2>;
130 #address-cells = <1>;
131 #size-cells = <0>;
132
133 switch1: switch1@0 {
134 compatible = "marvell,mv88e6190";
135 reg = <0>;
136 dsa,member = <0 1>;
137 eeprom-length = <65536>;
138
139 ports {
140 #address-cells = <1>;
141 #size-cells = <0>;
142
143 port@1 {
144 reg = <1>;
145 label = "eth_cu_1000_3";
146 };
147
148 port@2 {
149 reg = <2>;
150 label = "eth_cu_100_2";
151 };
152
153 port@3 {
154 reg = <3>;
155 label = "eth_cu_100_3";
156 };
157
158 switch1port9: port@9 {
159 reg = <9>;
160 label = "dsa";
161 phy-mode = "xgmii";
162 link = <&switch3port10
163 &switch2port10>;
164
165 fixed-link {
166 speed = <10000>;
167 full-duplex;
168 };
169 };
170
171 switch1port10: port@10 {
172 reg = <10>;
173 label = "dsa";
174 phy-mode = "xgmii";
175 link = <&switch0port10>;
176
177 fixed-link {
178 speed = <10000>;
179 full-duplex;
180 };
181 };
182 };
183 };
184 };
185
186 mdio_mux_4: mdio@4 {
187 reg = <4>;
188 #address-cells = <1>;
189 #size-cells = <0>;
190
191 switch2: switch2@0 {
192 compatible = "marvell,mv88e6190";
193 reg = <0>;
194 dsa,member = <0 2>;
195 eeprom-length = <65536>;
196
197 ports {
198 #address-cells = <1>;
199 #size-cells = <0>;
200
201 port@2 {
202 reg = <2>;
203 label = "eth_fc_1000_2";
204 phy-mode = "1000base-x";
205 managed = "in-band-status";
206 sfp = <&sff1>;
207 };
208
209 port@3 {
210 reg = <3>;
211 label = "eth_fc_1000_3";
212 phy-mode = "1000base-x";
213 managed = "in-band-status";
214 sfp = <&sff2>;
215 };
216
217 port@4 {
218 reg = <4>;
219 label = "eth_fc_1000_4";
220 phy-mode = "1000base-x";
221 managed = "in-band-status";
222 sfp = <&sff3>;
223 };
224
225 port@5 {
226 reg = <5>;
227 label = "eth_fc_1000_5";
228 phy-mode = "1000base-x";
229 managed = "in-band-status";
230 sfp = <&sff4>;
231 };
232
233 port@6 {
234 reg = <6>;
235 label = "eth_fc_1000_6";
236 phy-mode = "1000base-x";
237 managed = "in-band-status";
238 sfp = <&sff5>;
239 };
240
241 port@7 {
242 reg = <7>;
243 label = "eth_fc_1000_7";
244 phy-mode = "1000base-x";
245 managed = "in-band-status";
246 sfp = <&sff6>;
247 };
248
249 port@9 {
250 reg = <9>;
251 label = "eth_fc_1000_1";
252 phy-mode = "1000base-x";
253 managed = "in-band-status";
254 sfp = <&sff0>;
255 };
256
257 switch2port10: port@10 {
258 reg = <10>;
259 label = "dsa";
260 phy-mode = "2500base-x";
261 link = <&switch3port9
262 &switch1port9
263 &switch0port10>;
264
265 fixed-link {
266 speed = <2500>;
267 full-duplex;
268 };
269 };
270 };
271 };
272 };
273
274 mdio_mux_8: mdio@8 {
275 reg = <8>;
276 #address-cells = <1>;
277 #size-cells = <0>;
278
279 switch3: switch3@0 {
280 compatible = "marvell,mv88e6190";
281 reg = <0>;
282 dsa,member = <0 3>;
283 eeprom-length = <65536>;
284
285 ports {
286 #address-cells = <1>;
287 #size-cells = <0>;
288
289 port@2 {
290 reg = <2>;
291 label = "eth_fc_1000_8";
292 phy-mode = "1000base-x";
293 managed = "in-band-status";
294 sfp = <&sff7>;
295 };
296
297 port@3 {
298 reg = <3>;
299 label = "eth_fc_1000_9";
300 phy-mode = "1000base-x";
301 managed = "in-band-status";
302 sfp = <&sff8>;
303 };
304
305 port@4 {
306 reg = <4>;
307 label = "eth_fc_1000_10";
308 phy-mode = "1000base-x";
309 managed = "in-band-status";
310 sfp = <&sff9>;
311 };
312
313 switch3port9: port@9 {
314 reg = <9>;
315 label = "dsa";
316 phy-mode = "2500base-x";
317 link = <&switch2port10>;
318
319 fixed-link {
320 speed = <2500>;
321 full-duplex;
322 };
323 };
324
325 switch3port10: port@10 {
326 reg = <10>;
327 label = "dsa";
328 phy-mode = "xgmii";
329 link = <&switch1port9
330 &switch0port10>;
331
332 fixed-link {
333 speed = <10000>;
334 full-duplex;
335 };
336 };
337 };
338 };
339 };
340 };
341
342 sff0: sff0 {
343 compatible = "sff,sff";
344 i2c-bus = <&sff0_i2c>;
345 los-gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>;
346 tx-disable-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
347 };
348
349 sff1: sff1 {
350 compatible = "sff,sff";
351 i2c-bus = <&sff1_i2c>;
352 los-gpios = <&gpio9 1 GPIO_ACTIVE_HIGH>;
353 tx-disable-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
354 };
355
356 sff2: sff2 {
357 compatible = "sff,sff";
358 i2c-bus = <&sff2_i2c>;
359 los-gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>;
360 tx-disable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
361 };
362
363 sff3: sff3 {
364 compatible = "sff,sff";
365 i2c-bus = <&sff3_i2c>;
366 los-gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>;
367 tx-disable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
368 };
369
370 sff4: sff4 {
371 compatible = "sff,sff";
372 i2c-bus = <&sff4_i2c>;
373 los-gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>;
374 tx-disable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
375 };
376
377 sff5: sff5 {
378 compatible = "sff,sff";
379 i2c-bus = <&sff5_i2c>;
380 los-gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>;
381 tx-disable-gpios = <&gpio7 5 GPIO_ACTIVE_HIGH>;
382 };
383
384 sff6: sff6 {
385 compatible = "sff,sff";
386 i2c-bus = <&sff6_i2c>;
387 los-gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>;
388 tx-disable-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
389 };
390
391 sff7: sff7 {
392 compatible = "sff,sff";
393 i2c-bus = <&sff7_i2c>;
394 los-gpios = <&gpio9 7 GPIO_ACTIVE_HIGH>;
395 tx-disable-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>;
396 };
397
398 sff8: sff8 {
399 compatible = "sff,sff";
400 i2c-bus = <&sff8_i2c>;
401 los-gpios = <&gpio9 8 GPIO_ACTIVE_HIGH>;
402 tx-disable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
403 };
404
405 sff9: sff9 {
406 compatible = "sff,sff";
407 i2c-bus = <&sff9_i2c>;
408 los-gpios = <&gpio9 9 GPIO_ACTIVE_HIGH>;
409 tx-disable-gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
410 };
411
412 reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
413 compatible = "regulator-fixed";
414 regulator-name = "vcc_3v3_mcu";
415 regulator-min-microvolt = <3300000>;
416 regulator-max-microvolt = <3300000>;
417 };
418};
419
420&dspi0 {
421 pinctrl-0 = <&pinctrl_dspi0>;
422 pinctrl-names = "default";
423 bus-num = <0>;
424 status = "okay";
425
426 adc@5 {
427 compatible = "holt,hi8435";
428 reg = <5>;
429 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
430 spi-max-frequency = <1000000>;
431 };
432};
433
434&dspi1 {
435 bus-num = <1>;
436 pinctrl-names = "default";
437 pinctrl-0 = <&pinctrl_dspi1>;
438 status = "okay";
439
440 flash@0 {
441 #address-cells = <1>;
442 #size-cells = <1>;
443 compatible = "jedec,spi-nor";
444 reg = <0>;
445 spi-max-frequency = <50000000>;
446
447 partition@0 {
448 label = "m25p128-0";
449 reg = <0x0 0x01000000>;
450 };
451 };
452
453 flash@1 {
454 #address-cells = <1>;
455 #size-cells = <1>;
456 compatible = "jedec,spi-nor";
457 reg = <1>;
458 spi-max-frequency = <50000000>;
459
460 partition@0 {
461 label = "m25p128-1";
462 reg = <0x0 0x01000000>;
463 };
464 };
465};
466
467&adc0 {
468 vref-supply = <&reg_vcc_3v3_mcu>;
469 status = "okay";
470};
471
472&adc1 {
473 vref-supply = <&reg_vcc_3v3_mcu>;
474 status = "okay";
475};
476
477&edma0 {
478 status = "okay";
479};
480
481&edma1 {
482 status = "okay";
483};
484
485&esdhc0 {
486 pinctrl-names = "default";
487 pinctrl-0 = <&pinctrl_esdhc0>;
488 bus-width = <8>;
489 non-removable;
490 no-1-8-v;
491 no-sd;
492 no-sdio;
493 keep-power-in-suspend;
494 status = "okay";
495};
496
497&esdhc1 {
498 pinctrl-names = "default";
499 pinctrl-0 = <&pinctrl_esdhc1>;
500 bus-width = <4>;
501 no-sdio;
502 status = "okay";
503};
504
505&fec1 {
506 phy-mode = "rmii";
507 pinctrl-names = "default";
508 pinctrl-0 = <&pinctrl_fec1>;
509 status = "okay";
510
511 fixed-link {
512 speed = <100>;
513 full-duplex;
514 };
515
516 mdio1: mdio {
517 #address-cells = <1>;
518 #size-cells = <0>;
519 };
520};
521
522&i2c0 {
523 clock-frequency = <100000>;
524 pinctrl-names = "default";
525 pinctrl-0 = <&pinctrl_i2c0>;
526 status = "okay";
527
528 gpio5: io-expander@20 {
529 compatible = "nxp,pca9554";
530 reg = <0x20>;
531 gpio-controller;
532 #gpio-cells = <2>;
533 };
534
535 gpio6: io-expander@22 {
536 compatible = "nxp,pca9554";
537 reg = <0x22>;
538 gpio-controller;
539 #gpio-cells = <2>;
540 };
541
542 temp-sensor@48 {
543 compatible = "national,lm75";
544 reg = <0x48>;
545 };
546
547 eeprom@50 {
548 compatible = "atmel,24c04";
549 reg = <0x50>;
550 };
551
552 eeprom@52 {
553 compatible = "atmel,24c04";
554 reg = <0x52>;
555 };
556
557 elapsed-time-recorder@6b {
558 compatible = "dallas,ds1682";
559 reg = <0x6b>;
560 };
561};
562
563&i2c1 {
564 clock-frequency = <100000>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&pinctrl_i2c1>;
567 status = "okay";
568
569 watchdog@38 {
570 compatible = "zii,rave-wdt";
571 reg = <0x38>;
572 };
573
574 adc@4a {
575 compatible = "adi,adt7411";
576 reg = <0x4a>;
577 };
578};
579
580&i2c2 {
581 clock-frequency = <100000>;
582 pinctrl-names = "default";
583 pinctrl-0 = <&pinctrl_i2c2>;
584 status = "okay";
585
586 gpio9: io-expander@20 {
587 compatible = "semtech,sx1503q";
588 pinctrl-names = "default";
589 pinctrl-0 = <&pinctrl_sx1503_20>;
590 #gpio-cells = <2>;
591 reg = <0x20>;
592 gpio-controller;
593 interrupt-parent = <&gpio1>;
594 interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
595 };
596
597 temp-sensor@4e {
598 compatible = "national,lm75";
599 reg = <0x4e>;
600 };
601
602 temp-sensor@4f {
603 compatible = "national,lm75";
604 reg = <0x4f>;
605 };
606
607 gpio7: io-expander@23 {
608 compatible = "nxp,pca9555";
609 gpio-controller;
610 #gpio-cells = <2>;
611 reg = <0x23>;
612 };
613
614 adc@4a {
615 compatible = "adi,adt7411";
616 reg = <0x4a>;
617 };
618
619 eeprom@54 {
620 compatible = "atmel,24c08";
621 reg = <0x54>;
622 };
623
624 i2c-mux@70 {
625 compatible = "nxp,pca9548";
626 pinctrl-names = "default";
627 #address-cells = <1>;
628 #size-cells = <0>;
629 reg = <0x70>;
630 i2c-mux-idle-disconnect;
631
632 sff0_i2c: i2c@1 {
633 #address-cells = <1>;
634 #size-cells = <0>;
635 reg = <1>;
636 };
637
638 sff1_i2c: i2c@2 {
639 #address-cells = <1>;
640 #size-cells = <0>;
641 reg = <2>;
642 };
643
644 sff2_i2c: i2c@3 {
645 #address-cells = <1>;
646 #size-cells = <0>;
647 reg = <3>;
648 };
649
650 sff3_i2c: i2c@4 {
651 #address-cells = <1>;
652 #size-cells = <0>;
653 reg = <4>;
654 };
655
656 sff4_i2c: i2c@5 {
657 #address-cells = <1>;
658 #size-cells = <0>;
659 reg = <5>;
660 };
661 };
662
663 i2c-mux@71 {
664 compatible = "nxp,pca9548";
665 pinctrl-names = "default";
666 reg = <0x71>;
667 #address-cells = <1>;
668 #size-cells = <0>;
669 i2c-mux-idle-disconnect;
670
671 sff5_i2c: i2c@1 {
672 #address-cells = <1>;
673 #size-cells = <0>;
674 reg = <1>;
675 };
676
677 sff6_i2c: i2c@2 {
678 #address-cells = <1>;
679 #size-cells = <0>;
680 reg = <2>;
681 };
682
683 sff7_i2c: i2c@3 {
684 #address-cells = <1>;
685 #size-cells = <0>;
686 reg = <3>;
687 };
688
689 sff8_i2c: i2c@4 {
690 #address-cells = <1>;
691 #size-cells = <0>;
692 reg = <4>;
693 };
694
695 sff9_i2c: i2c@5 {
696 #address-cells = <1>;
697 #size-cells = <0>;
698 reg = <5>;
699 };
700 };
701};
702
703&snvsrtc {
704 status = "disabled";
705};
706
707&uart0 {
708 pinctrl-names = "default";
709 pinctrl-0 = <&pinctrl_uart0>;
710 status = "okay";
711};
712
713&uart1 {
714 linux,rs485-enabled-at-boot-time;
715 pinctrl-names = "default";
716 pinctrl-0 = <&pinctrl_uart1>;
717 status = "okay";
718};
719
720&uart2 {
721 linux,rs485-enabled-at-boot-time;
722 pinctrl-names = "default";
723 pinctrl-0 = <&pinctrl_uart2>;
724 status = "okay";
725};
726
727&iomuxc {
728 pinctrl_dspi0: dspi0grp {
729 fsl,pins = <
730 VF610_PAD_PTB19__DSPI0_CS0 0x1182
731 VF610_PAD_PTB18__DSPI0_CS1 0x1182
732 VF610_PAD_PTB13__DSPI0_CS4 0x1182
733 VF610_PAD_PTB12__DSPI0_CS5 0x1182
734 VF610_PAD_PTB20__DSPI0_SIN 0x1181
735 VF610_PAD_PTB21__DSPI0_SOUT 0x1182
736 VF610_PAD_PTB22__DSPI0_SCK 0x1182
737 >;
738 };
739
740 pinctrl_dspi1: dspi1grp {
741 fsl,pins = <
742 VF610_PAD_PTD5__DSPI1_CS0 0x1182
743 VF610_PAD_PTD4__DSPI1_CS1 0x1182
744 VF610_PAD_PTC6__DSPI1_SIN 0x1181
745 VF610_PAD_PTC7__DSPI1_SOUT 0x1182
746 VF610_PAD_PTC8__DSPI1_SCK 0x1182
747 >;
748 };
749
750 pinctrl_dspi2: dspi2gpio {
751 fsl,pins = <
752 VF610_PAD_PTD30__GPIO_64 0x33e2
753 VF610_PAD_PTD29__GPIO_65 0x33e1
754 VF610_PAD_PTD28__GPIO_66 0x33e2
755 VF610_PAD_PTD27__GPIO_67 0x33e2
756 VF610_PAD_PTD26__GPIO_68 0x31c2
757 >;
758 };
759
760 pinctrl_esdhc0: esdhc0grp {
761 fsl,pins = <
762 VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
763 VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
764 VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
765 VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
766 VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
767 VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
768 VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
769 VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
770 VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
771 VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
772 >;
773 };
774
775 pinctrl_esdhc1: esdhc1grp {
776 fsl,pins = <
777 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
778 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
779 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
780 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
781 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
782 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
783 >;
784 };
785
786 pinctrl_fec1: fec1grp {
787 fsl,pins = <
788 VF610_PAD_PTA6__RMII_CLKIN 0x30d1
789 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
790 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
791 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
792 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
793 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
794 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
795 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
796 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
797 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
798 >;
799 };
800
801 pinctrl_i2c0: i2c0grp {
802 fsl,pins = <
803 VF610_PAD_PTB14__I2C0_SCL 0x37ff
804 VF610_PAD_PTB15__I2C0_SDA 0x37ff
805 >;
806 };
807
808 pinctrl_i2c1: i2c1grp {
809 fsl,pins = <
810 VF610_PAD_PTB16__I2C1_SCL 0x37ff
811 VF610_PAD_PTB17__I2C1_SDA 0x37ff
812 >;
813 };
814
815 pinctrl_i2c2: i2c2grp {
816 fsl,pins = <
817 VF610_PAD_PTA22__I2C2_SCL 0x37ff
818 VF610_PAD_PTA23__I2C2_SDA 0x37ff
819 >;
820 };
821
822 pinctrl_leds_debug: pinctrl-leds-debug {
823 fsl,pins = <
824 VF610_PAD_PTB26__GPIO_96 0x31c2
825 >;
826 };
827
828 pinctrl_mdio_mux: pinctrl-mdio-mux {
829 fsl,pins = <
830 VF610_PAD_PTE27__GPIO_132 0x31c2
831 VF610_PAD_PTE28__GPIO_133 0x31c2
832 VF610_PAD_PTE21__GPIO_126 0x31c2
833 VF610_PAD_PTE22__GPIO_127 0x31c2
834 >;
835 };
836
837 pinctrl_qspi0: qspi0grp {
838 fsl,pins = <
839 VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3
840 VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff
841 VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3
842 VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3
843 VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3
844 VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3
845 >;
846 };
847
848 pinctrl_sx1503_20: pinctrl-sx1503-20 {
849 fsl,pins = <
850 VF610_PAD_PTD31__GPIO_63 0x219d
851 >;
852 };
853
854 pinctrl_uart0: uart0grp {
855 fsl,pins = <
856 VF610_PAD_PTB10__UART0_TX 0x21a2
857 VF610_PAD_PTB11__UART0_RX 0x21a1
858 >;
859 };
860
861 pinctrl_uart1: uart1grp {
862 fsl,pins = <
863 VF610_PAD_PTB23__UART1_TX 0x21a2
864 VF610_PAD_PTB24__UART1_RX 0x21a1
865 VF610_PAD_PTB25__UART1_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */
866 >;
867 };
868
869 pinctrl_uart2: uart2grp {
870 fsl,pins = <
871 VF610_PAD_PTD0__UART2_TX 0x21a2
872 VF610_PAD_PTD1__UART2_RX 0x21a1
873 VF610_PAD_PTD2__UART2_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */
874 >;
875 };
876};