blob: 7eda63d5682f135beff6d86a31f3a6d92ad36d1e [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/mediatek/mtk-svs.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Smart Voltage Scaling (SVS)
8
9maintainers:
10 - Roger Lu <roger.lu@mediatek.com>
11 - Matthias Brugger <matthias.bgg@gmail.com>
12 - Kevin Hilman <khilman@kernel.org>
13
14description: |+
15 The SVS engine is a piece of hardware which has several
16 controllers(banks) for calculating suitable voltage to
17 different power domains(CPU/GPU/CCI) according to
18 chip process corner, temperatures and other factors. Then DVFS
19 driver could apply SVS bank voltage to PMIC/Buck.
20
21properties:
22 compatible:
23 enum:
24 - mediatek,mt8183-svs
25 - mediatek,mt8188-svs
26 - mediatek,mt8192-svs
27
28 reg:
29 maxItems: 1
30 description: Address range of the MTK SVS controller.
31
32 interrupts:
33 maxItems: 1
34
35 clocks:
36 maxItems: 1
37 description: Main clock for MTK SVS controller to work.
38
39 clock-names:
40 const: main
41
42 nvmem-cells:
43 minItems: 1
44 description:
45 Phandle to the calibration data provided by a nvmem device.
46 items:
47 - description: SVS efuse for SVS controller
48 - description: Thermal efuse for SVS controller
49
50 nvmem-cell-names:
51 items:
52 - const: svs-calibration-data
53 - const: t-calibration-data
54
55 resets:
56 maxItems: 1
57
58 reset-names:
59 items:
60 - const: svs_rst
61
62required:
63 - compatible
64 - reg
65 - interrupts
66 - clocks
67 - clock-names
68 - nvmem-cells
69 - nvmem-cell-names
70
71additionalProperties: false
72
73examples:
74 - |
75 #include <dt-bindings/clock/mt8183-clk.h>
76 #include <dt-bindings/interrupt-controller/arm-gic.h>
77 #include <dt-bindings/interrupt-controller/irq.h>
78
79 soc {
80 #address-cells = <2>;
81 #size-cells = <2>;
82
83 svs@1100b000 {
84 compatible = "mediatek,mt8183-svs";
85 reg = <0 0x1100b000 0 0x1000>;
86 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
87 clocks = <&infracfg CLK_INFRA_THERM>;
88 clock-names = "main";
89 nvmem-cells = <&svs_calibration>, <&thermal_calibration>;
90 nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
91 };
92 };