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git01.mediatek.com / filogic / uboot / 53633a893a06bd5a0c807287d9cc29337806eaf7 / . / Bindings / pinctrl / qcom,sdm630-pinctrl.yaml
blob: 508e0633b253e4a8ae12e54334cf7fb5f421f1b6 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame^]1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sdm630-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SDM630 and SDM660 TLMM pin controller
8
9maintainers:
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
13description:
14 Top Level Mode Multiplexer pin controller in Qualcomm SDM630 and SDM660 SoC.
15
16allOf:
17 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
18
19properties:
20 compatible:
21 enum:
22 - qcom,sdm630-pinctrl
23 - qcom,sdm660-pinctrl
24
25 reg:
26 maxItems: 3
27
28 reg-names:
29 items:
30 - const: south
31 - const: center
32 - const: north
33
34 interrupts:
35 maxItems: 1
36
37 interrupt-controller: true
38 "#interrupt-cells": true
39 gpio-controller: true
40
41 gpio-reserved-ranges:
42 minItems: 1
43 maxItems: 57
44
45 gpio-line-names:
46 maxItems: 114
47
48 "#gpio-cells": true
49 gpio-ranges: true
50 wakeup-parent: true
51
52patternProperties:
53 "-state$":
54 oneOf:
55 - $ref: "#/$defs/qcom-sdm630-tlmm-state"
56 - patternProperties:
57 "-pins$":
58 $ref: "#/$defs/qcom-sdm630-tlmm-state"
59 additionalProperties: false
60
61$defs:
62 qcom-sdm630-tlmm-state:
63 type: object
64 description:
65 Pinctrl node's client devices use subnodes for desired pin configuration.
66 Client device subnodes use below standard properties.
67 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
68 unevaluatedProperties: false
69
70 properties:
71 pins:
72 description:
73 List of gpio pins affected by the properties specified in this
74 subnode.
75 items:
76 oneOf:
77 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-3])$"
78 - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
79 sdc2_cmd, sdc2_data ]
80 minItems: 1
81 maxItems: 36
82
83 function:
84 description:
85 Specify the alternative function to be configured for the specified
86 pins.
87 enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,
88 atest_char2, atest_char3, atest_gpsadc0, atest_gpsadc1,
89 atest_tsens, atest_tsens2, atest_usb1, atest_usb10,
90 atest_usb11, atest_usb12, atest_usb13, atest_usb2, atest_usb20,
91 atest_usb21, atest_usb22, atest_usb23, audio_ref, bimc_dte0,
92 bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4,
93 blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8_a, blsp_i2c8_b,
94 blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2,
95 blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8_a,
96 blsp_spi8_b, blsp_spi8_cs1, blsp_spi8_cs2, blsp_uart1,
97 blsp_uart2, blsp_uart5, blsp_uart6_a, blsp_uart6_b, blsp_uim1,
98 blsp_uim2, blsp_uim5, blsp_uim6, cam_mclk, cci_async, cci_i2c,
99 cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, gcc_gp1,
100 gcc_gp2, gcc_gp3, gpio, gps_tx_a, gps_tx_b, gps_tx_c,
101 isense_dbg, jitter_bist, ldo_en, ldo_update, m_voc, mdp_vsync,
102 mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3, mss_lte,
103 nav_pps_a, nav_pps_b, nav_pps_c, pa_indicator, phase_flag0,
104 phase_flag1, phase_flag10, phase_flag11, phase_flag12,
105 phase_flag13, phase_flag14, phase_flag15, phase_flag16,
106 phase_flag17, phase_flag18, phase_flag19, phase_flag2,
107 phase_flag20, phase_flag21, phase_flag22, phase_flag23,
108 phase_flag24, phase_flag25, phase_flag26, phase_flag27,
109 phase_flag28, phase_flag29, phase_flag3, phase_flag30,
110 phase_flag31, phase_flag4, phase_flag5, phase_flag6,
111 phase_flag7, phase_flag8, phase_flag9, pll_bypassnl, pll_reset,
112 pri_mi2s, pri_mi2s_ws, prng_rosc, pwr_crypto, pwr_modem,
113 pwr_nav, qdss_cti0_a, qdss_cti0_b, qdss_cti1_a, qdss_cti1_b,
114 qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11,
115 qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15, qdss_gpio2,
116 qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, qdss_gpio7,
117 qdss_gpio8, qdss_gpio9, qlink_enable, qlink_request, qspi_clk,
118 qspi_cs, qspi_data0, qspi_data1, qspi_data2, qspi_data3,
119 qspi_resetn, sec_mi2s, sndwire_clk, sndwire_data, sp_cmu,
120 ssc_irq, tgu_ch0, tgu_ch1, tsense_pwm1, tsense_pwm2, uim1_clk,
121 uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
122 uim2_present, uim2_reset, uim_batt, vfr_1, vsense_clkout,
123 vsense_data0, vsense_data1, vsense_mode, wlan1_adc0,
124 wlan1_adc1, wlan2_adc0, wlan2_adc1 ]
125
126 required:
127 - pins
128
129required:
130 - compatible
131 - reg
132
133additionalProperties: false
134
135examples:
136 - |
137 #include <dt-bindings/interrupt-controller/arm-gic.h>
138
139 tlmm: pinctrl@3100000 {
140 compatible = "qcom,sdm630-pinctrl";
141 reg = <0x03100000 0x400000>,
142 <0x03500000 0x400000>,
143 <0x03900000 0x400000>;
144 reg-names = "south", "center", "north";
145 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
146 gpio-controller;
147 gpio-ranges = <&tlmm 0 0 114>;
148 #gpio-cells = <2>;
149 interrupt-controller;
150 #interrupt-cells = <2>;
151
152 blsp1-uart1-default-state {
153 pins = "gpio0", "gpio1", "gpio2", "gpio3";
154 function = "gpio";
155 drive-strength = <2>;
156 bias-disable;
157 };
158
159 blsp2_uart1_default: blsp2-uart1-active-state {
160 tx-rts-pins {
161 pins = "gpio16", "gpio19";
162 function = "blsp_uart5";
163 drive-strength = <2>;
164 bias-disable;
165 };
166
167 rx-pins {
168 pins = "gpio17";
169 function = "blsp_uart5";
170 drive-strength = <2>;
171 bias-pull-up;
172 };
173
174 cts-pins {
175 pins = "gpio18";
176 function = "blsp_uart5";
177 drive-strength = <2>;
178 bias-pull-down;
179 };
180 };
181 };