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git01.mediatek.com / filogic / uboot / 53633a893a06bd5a0c807287d9cc29337806eaf7 / . / Bindings / media / rockchip-isp1.yaml
blob: e466dff8286d2bbaa2b111ee3c0a26166525ac4c [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame^]1# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/rockchip-isp1.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip SoC Image Signal Processing unit v1
8
9maintainers:
10 - Helen Koike <helen.koike@collabora.com>
11
12description: |
13 Rockchip ISP1 is the Camera interface for the Rockchip series of SoCs
14 which contains image processing, scaling, and compression functions.
15
16properties:
17 compatible:
18 enum:
19 - rockchip,px30-cif-isp
20 - rockchip,rk3399-cif-isp
21
22 reg:
23 maxItems: 1
24
25 interrupts:
26 minItems: 1
27 maxItems: 3
28
29 interrupt-names:
30 items:
31 - const: isp
32 - const: mi
33 - const: mipi
34
35 clocks:
36 minItems: 3
37 items:
38 # isp0 and isp1
39 - description: ISP clock
40 - description: ISP AXI clock
41 - description: ISP AHB clock
42 # only for isp1
43 - description: ISP Pixel clock
44
45 clock-names:
46 minItems: 3
47 items:
48 # isp0 and isp1
49 - const: isp
50 - const: aclk
51 - const: hclk
52 # only for isp1
53 - const: pclk
54
55 iommus:
56 maxItems: 1
57
58 phys:
59 maxItems: 1
60 description: phandle for the PHY port
61
62 phy-names:
63 const: dphy
64
65 power-domains:
66 maxItems: 1
67
68 ports:
69 $ref: /schemas/graph.yaml#/properties/ports
70
71 properties:
72 port@0:
73 $ref: /schemas/graph.yaml#/$defs/port-base
74 unevaluatedProperties: false
75 description: connection point for sensors at MIPI-DPHY RX0
76
77 properties:
78 endpoint:
79 $ref: video-interfaces.yaml#
80 unevaluatedProperties: false
81
82 properties:
83 data-lanes:
84 minItems: 1
85 maxItems: 4
86
87 port@1:
88 $ref: /schemas/graph.yaml#/$defs/port-base
89 unevaluatedProperties: false
90 description: connection point for input on the parallel interface
91
92 properties:
93 bus-type:
94 enum: [5, 6]
95
96 endpoint:
97 $ref: video-interfaces.yaml#
98 unevaluatedProperties: false
99
100 required:
101 - bus-type
102
103 anyOf:
104 - required:
105 - port@0
106 - required:
107 - port@1
108
109required:
110 - compatible
111 - reg
112 - interrupts
113 - clocks
114 - clock-names
115 - iommus
116 - phys
117 - phy-names
118 - power-domains
119 - ports
120
121allOf:
122 - if:
123 properties:
124 compatible:
125 contains:
126 const: rockchip,rk3399-cif-isp
127 then:
128 properties:
129 clocks:
130 minItems: 3
131 maxItems: 4
132 clock-names:
133 minItems: 3
134 maxItems: 4
135
136 - if:
137 properties:
138 compatible:
139 contains:
140 const: rockchip,px30-cif-isp
141 then:
142 required:
143 - interrupt-names
144
145additionalProperties: false
146
147examples:
148 - |
149
150 #include <dt-bindings/clock/rk3399-cru.h>
151 #include <dt-bindings/interrupt-controller/arm-gic.h>
152 #include <dt-bindings/power/rk3399-power.h>
153
154 parent0: parent {
155 #address-cells = <2>;
156 #size-cells = <2>;
157
158 isp0: isp0@ff910000 {
159 compatible = "rockchip,rk3399-cif-isp";
160 reg = <0x0 0xff910000 0x0 0x4000>;
161 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
162 clocks = <&cru SCLK_ISP0>,
163 <&cru ACLK_ISP0_WRAPPER>,
164 <&cru HCLK_ISP0_WRAPPER>;
165 clock-names = "isp", "aclk", "hclk";
166 iommus = <&isp0_mmu>;
167 phys = <&dphy>;
168 phy-names = "dphy";
169 power-domains = <&power RK3399_PD_ISP0>;
170
171 ports {
172 #address-cells = <1>;
173 #size-cells = <0>;
174
175 port@0 {
176 reg = <0>;
177 #address-cells = <1>;
178 #size-cells = <0>;
179
180 mipi_in_wcam: endpoint@0 {
181 reg = <0>;
182 remote-endpoint = <&wcam_out>;
183 data-lanes = <1 2>;
184 };
185
186 mipi_in_ucam: endpoint@1 {
187 reg = <1>;
188 remote-endpoint = <&ucam_out>;
189 data-lanes = <1>;
190 };
191 };
192 };
193 };
194
195 i2c7: i2c {
196 #address-cells = <1>;
197 #size-cells = <0>;
198
199 wcam: camera@36 {
200 compatible = "ovti,ov5695";
201 reg = <0x36>;
202 clocks = <&cru SCLK_TESTCLKOUT1>;
203
204 port {
205 wcam_out: endpoint {
206 remote-endpoint = <&mipi_in_wcam>;
207 data-lanes = <1 2>;
208 };
209 };
210 };
211
212 ucam: camera@3c {
213 compatible = "ovti,ov2685";
214 reg = <0x3c>;
215
216 clocks = <&cru SCLK_TESTCLKOUT1>;
217 clock-names = "xvclk";
218
219 avdd-supply = <&pp2800_cam>;
220 dovdd-supply = <&pp1800>;
221 dvdd-supply = <&pp1800>;
222
223 port {
224 ucam_out: endpoint {
225 remote-endpoint = <&mipi_in_ucam>;
226 data-lanes = <1>;
227 };
228 };
229 };
230 };
231 };
232
233 - |
234
235 #include <dt-bindings/interrupt-controller/arm-gic.h>
236 #include <dt-bindings/power/px30-power.h>
237
238 parent1: parent {
239 #address-cells = <2>;
240 #size-cells = <2>;
241
242 isp: isp@ff4a0000 {
243 compatible = "rockchip,px30-cif-isp";
244 reg = <0x0 0xff4a0000 0x0 0x8000>;
245 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
248 interrupt-names = "isp", "mi", "mipi";
249 clocks = <&cru SCLK_ISP0>,
250 <&cru ACLK_ISP0_WRAPPER>,
251 <&cru HCLK_ISP0_WRAPPER>,
252 <&cru PCLK_ISP1_WRAPPER>;
253 clock-names = "isp", "aclk", "hclk", "pclk";
254 iommus = <&isp_mmu>;
255 phys = <&csi_dphy>;
256 phy-names = "dphy";
257 power-domains = <&power PX30_PD_VI>;
258
259 ports {
260 #address-cells = <1>;
261 #size-cells = <0>;
262
263 port@0 {
264 reg = <0>;
265 #address-cells = <1>;
266 #size-cells = <0>;
267
268 mipi_in_ucam1: endpoint@0 {
269 reg = <0>;
270 remote-endpoint = <&ucam1_out>;
271 data-lanes = <1 2>;
272 };
273 };
274 };
275 };
276
277 i2c2: i2c {
278 #address-cells = <1>;
279 #size-cells = <0>;
280
281 ov5695: camera@36 {
282 compatible = "ovti,ov5647";
283 reg = <0x36>;
284 clocks = <&cru SCLK_CIF_OUT>;
285
286 port {
287 ucam1_out: endpoint {
288 remote-endpoint = <&mipi_in_ucam1>;
289 data-lanes = <1 2>;
290 };
291 };
292 };
293 };
294 };