| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame^] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Loongson Local I/O Interrupt Controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Jiaxun Yang <jiaxun.yang@flygoat.com> |
| 11 | |
| 12 | description: | |
| 13 | This interrupt controller is found in the Loongson-3 family of chips and |
| 14 | Loongson-2K1000 chip, as the primary package interrupt controller which |
| 15 | can route local I/O interrupt to interrupt lines of cores. |
| 16 | |
| 17 | allOf: |
| 18 | - $ref: /schemas/interrupt-controller.yaml# |
| 19 | |
| 20 | properties: |
| 21 | compatible: |
| 22 | enum: |
| 23 | - loongson,liointc-1.0 |
| 24 | - loongson,liointc-1.0a |
| 25 | - loongson,liointc-2.0 |
| 26 | |
| 27 | reg: |
| 28 | minItems: 1 |
| 29 | maxItems: 3 |
| 30 | |
| 31 | reg-names: |
| 32 | items: |
| 33 | - const: main |
| 34 | - const: isr0 |
| 35 | - const: isr1 |
| 36 | |
| 37 | interrupt-controller: true |
| 38 | |
| 39 | interrupts: |
| 40 | description: |
| 41 | Interrupt source of the CPU interrupts. |
| 42 | minItems: 1 |
| 43 | maxItems: 4 |
| 44 | |
| 45 | interrupt-names: |
| 46 | description: List of names for the parent interrupts. |
| 47 | items: |
| 48 | - const: int0 |
| 49 | - const: int1 |
| 50 | - const: int2 |
| 51 | - const: int3 |
| 52 | minItems: 1 |
| 53 | |
| 54 | '#interrupt-cells': |
| 55 | const: 2 |
| 56 | |
| 57 | loongson,parent_int_map: |
| 58 | description: | |
| 59 | This property points how the children interrupts will be mapped into CPU |
| 60 | interrupt lines. Each cell refers to a parent interrupt line from 0 to 3 |
| 61 | and each bit in the cell refers to a child interrupt from 0 to 31. |
| 62 | If a CPU interrupt line didn't connect with liointc, then keep its |
| 63 | cell with zero. |
| 64 | $ref: /schemas/types.yaml#/definitions/uint32-array |
| 65 | minItems: 4 |
| 66 | maxItems: 4 |
| 67 | |
| 68 | required: |
| 69 | - compatible |
| 70 | - reg |
| 71 | - interrupts |
| 72 | - interrupt-controller |
| 73 | - '#interrupt-cells' |
| 74 | - loongson,parent_int_map |
| 75 | |
| 76 | |
| 77 | unevaluatedProperties: false |
| 78 | |
| 79 | if: |
| 80 | properties: |
| 81 | compatible: |
| 82 | contains: |
| 83 | enum: |
| 84 | - loongson,liointc-2.0 |
| 85 | |
| 86 | then: |
| 87 | properties: |
| 88 | reg: |
| 89 | minItems: 3 |
| 90 | |
| 91 | required: |
| 92 | - reg-names |
| 93 | |
| 94 | else: |
| 95 | properties: |
| 96 | reg: |
| 97 | maxItems: 1 |
| 98 | |
| 99 | examples: |
| 100 | - | |
| 101 | iointc: interrupt-controller@3ff01400 { |
| 102 | compatible = "loongson,liointc-1.0"; |
| 103 | reg = <0x3ff01400 0x64>; |
| 104 | |
| 105 | interrupt-controller; |
| 106 | #interrupt-cells = <2>; |
| 107 | |
| 108 | interrupt-parent = <&cpuintc>; |
| 109 | interrupts = <2>, <3>; |
| 110 | interrupt-names = "int0", "int1"; |
| 111 | |
| 112 | loongson,parent_int_map = <0xf0ffffff>, /* int0 */ |
| 113 | <0x0f000000>, /* int1 */ |
| 114 | <0x00000000>, /* int2 */ |
| 115 | <0x00000000>; /* int3 */ |
| 116 | |
| 117 | }; |
| 118 | |
| 119 | ... |