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git01.mediatek.com / filogic / uboot / 9310ff7867016eb1182bf34ae04405c336cbe948 / . / arch / arm / cpu / armv7 / omap4 / hwinit.c
blob: 78b3cabb07d8cd38e0fd1e0ef42d2c47392013ba [file] [log] [blame]
Sricharan9310ff72011-11-15 09:49:55 -0500[diff] [blame^]1/*
2 *
3 * Common functions for OMAP4 based boards
4 *
5 * (C) Copyright 2010
6 * Texas Instruments, <www.ti.com>
7 *
8 * Author :
9 * Aneesh V <aneesh@ti.com>
10 * Steve Sakoman <steve@sakoman.com>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30#include <common.h>
31#include <asm/armv7.h>
32#include <asm/arch/cpu.h>
33#include <asm/arch/sys_proto.h>
34#include <asm/sizes.h>
35#include <asm/arch/emif.h>
36#include <asm/arch/gpio.h>
37
38DECLARE_GLOBAL_DATA_PTR;
39
40u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
41
42static const struct gpio_bank gpio_bank_44xx[6] = {
43 { (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
44 { (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX },
45 { (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX },
46 { (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX },
47 { (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX },
48 { (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX },
49};
50
51const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
52
53#ifdef CONFIG_SPL_BUILD
54/*
55 * Some tuning of IOs for optimal power and performance
56 */
57void do_io_settings(void)
58{
59 u32 lpddr2io;
60 struct control_lpddr2io_regs *lpddr2io_regs =
61 (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
62 struct omap4_sys_ctrl_regs *const ctrl =
63 (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
64
65 u32 omap4_rev = omap_revision();
66
67 if (omap4_rev == OMAP4430_ES1_0)
68 lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
69 else if (omap4_rev == OMAP4430_ES2_0)
70 lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
71 else
72 lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
73
74 /* EMIF1 */
75 writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
76 writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
77 /* No pull for GR10 as per hw team's recommendation */
78 writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
79 &lpddr2io_regs->control_lpddr2io1_2);
80 writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3);
81
82 /* EMIF2 */
83 writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
84 writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
85 /* No pull for GR10 as per hw team's recommendation */
86 writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
87 &lpddr2io_regs->control_lpddr2io2_2);
88 writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3);
89
90 /*
91 * Some of these settings (TRIM values) come from eFuse and are
92 * in turn programmed in the eFuse at manufacturing time after
93 * calibration of the device. Do the software over-ride only if
94 * the device is not correctly trimmed
95 */
96 if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) {
97
98 writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
99 &ctrl->control_ldosram_iva_voltage_ctrl);
100
101 writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
102 &ctrl->control_ldosram_mpu_voltage_ctrl);
103
104 writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
105 &ctrl->control_ldosram_core_voltage_ctrl);
106 }
107
108 if (!readl(&ctrl->control_efuse_1))
109 writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);
110
111 if (!readl(&ctrl->control_efuse_2))
112 writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
113}
114#endif
115
116void init_omap_revision(void)
117{
118 /*
119 * For some of the ES2/ES1 boards ID_CODE is not reliable:
120 * Also, ES1 and ES2 have different ARM revisions
121 * So use ARM revision for identification
122 */
123 unsigned int arm_rev = cortex_rev();
124
125 switch (arm_rev) {
126 case MIDR_CORTEX_A9_R0P1:
127 *omap4_revision = OMAP4430_ES1_0;
128 break;
129 case MIDR_CORTEX_A9_R1P2:
130 switch (readl(CONTROL_ID_CODE)) {
131 case OMAP4_CONTROL_ID_CODE_ES2_0:
132 *omap4_revision = OMAP4430_ES2_0;
133 break;
134 case OMAP4_CONTROL_ID_CODE_ES2_1:
135 *omap4_revision = OMAP4430_ES2_1;
136 break;
137 case OMAP4_CONTROL_ID_CODE_ES2_2:
138 *omap4_revision = OMAP4430_ES2_2;
139 break;
140 default:
141 *omap4_revision = OMAP4430_ES2_0;
142 break;
143 }
144 break;
145 case MIDR_CORTEX_A9_R1P3:
146 *omap4_revision = OMAP4430_ES2_3;
147 break;
148 case MIDR_CORTEX_A9_R2P10:
149 *omap4_revision = OMAP4460_ES1_0;
150 break;
151 default:
152 *omap4_revision = OMAP4430_SILICON_ID_INVALID;
153 break;
154 }
155}
156
157#ifndef CONFIG_SYS_L2CACHE_OFF
158void v7_outer_cache_enable(void)
159{
160 set_pl310_ctrl_reg(1);
161}
162
163void v7_outer_cache_disable(void)
164{
165 set_pl310_ctrl_reg(0);
166}
167#endif