blob: b3e5f9c9138a46ce4702670a57482a479ea96b48 [file] [log] [blame]
Simon Glass7cf5fe02019-05-02 10:52:12 -06001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2018 Google, Inc
4 */
5
6#include <common.h>
7#include <debug_uart.h>
Simon Glass7b8a5582019-10-20 21:37:50 -06008#include <dm.h>
Simon Glassf11478f2019-12-28 10:45:07 -07009#include <hang.h>
Simon Glass2dc9c342020-05-10 11:40:01 -060010#include <image.h>
Simon Glass97589732020-05-10 11:40:02 -060011#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060012#include <log.h>
Simon Glass7cf5fe02019-05-02 10:52:12 -060013#include <spl.h>
14#include <asm/cpu.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060015#include <asm/global_data.h>
Simon Glass7cf5fe02019-05-02 10:52:12 -060016#include <asm/mtrr.h>
17#include <asm/processor.h>
18#include <asm-generic/sections.h>
19
20DECLARE_GLOBAL_DATA_PTR;
21
22__weak int arch_cpu_init_dm(void)
23{
24 return 0;
25}
26
27static int x86_tpl_init(void)
28{
29 int ret;
30
31 debug("%s starting\n", __func__);
Simon Glass81f14622019-10-20 21:37:55 -060032 ret = x86_cpu_init_tpl();
33 if (ret) {
34 debug("%s: x86_cpu_init_tpl() failed\n", __func__);
35 return ret;
36 }
Simon Glass7cf5fe02019-05-02 10:52:12 -060037 ret = spl_init();
38 if (ret) {
39 debug("%s: spl_init() failed\n", __func__);
40 return ret;
41 }
42 ret = arch_cpu_init();
43 if (ret) {
44 debug("%s: arch_cpu_init() failed\n", __func__);
45 return ret;
46 }
47 ret = arch_cpu_init_dm();
48 if (ret) {
49 debug("%s: arch_cpu_init_dm() failed\n", __func__);
50 return ret;
51 }
52 preloader_console_init();
Simon Glass7cf5fe02019-05-02 10:52:12 -060053
54 return 0;
55}
56
57void board_init_f(ulong flags)
58{
59 int ret;
60
61 ret = x86_tpl_init();
62 if (ret) {
63 debug("Error %d\n", ret);
Simon Glass11ba7142019-09-25 08:56:51 -060064 panic("x86_tpl_init fail");
Simon Glass7cf5fe02019-05-02 10:52:12 -060065 }
66
67 /* Uninit CAR and jump to board_init_f_r() */
68 board_init_r(gd, 0);
69}
70
71void board_init_f_r(void)
72{
73 /* Not used since we never call board_init_f_r_trampoline() */
74 while (1);
75}
76
77u32 spl_boot_device(void)
78{
Simon Glassd81f07f2020-11-04 09:57:35 -070079 return IS_ENABLED(CONFIG_CHROMEOS_VBOOT) ? BOOT_DEVICE_CROS_VBOOT :
Simon Glass19da9c42019-09-25 08:11:39 -060080 BOOT_DEVICE_SPI_MMAP;
Simon Glass7cf5fe02019-05-02 10:52:12 -060081}
82
83int spl_start_uboot(void)
84{
85 return 0;
86}
87
88void spl_board_announce_boot_device(void)
89{
90 printf("SPI flash");
91}
92
93static int spl_board_load_image(struct spl_image_info *spl_image,
94 struct spl_boot_device *bootdev)
95{
96 spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
97 spl_image->entry_point = CONFIG_SPL_TEXT_BASE;
98 spl_image->load_addr = CONFIG_SPL_TEXT_BASE;
99 spl_image->os = IH_OS_U_BOOT;
100 spl_image->name = "U-Boot";
101
102 debug("Loading to %lx\n", spl_image->load_addr);
103
104 return 0;
105}
Simon Glass19da9c42019-09-25 08:11:39 -0600106SPL_LOAD_IMAGE_METHOD("SPI", 5, BOOT_DEVICE_SPI_MMAP, spl_board_load_image);
Simon Glass7cf5fe02019-05-02 10:52:12 -0600107
108int spl_spi_load_image(void)
109{
110 return -EPERM;
111}
112
113void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
114{
Simon Glassc00af3e2021-01-24 10:06:11 -0700115 debug("Jumping to %s at %lx\n", spl_phase_name(spl_next_phase()),
116 (ulong)spl_image->entry_point);
117#ifdef DEBUG
118 print_buffer(spl_image->entry_point, (void *)spl_image->entry_point, 1,
119 0x20, 0);
120#endif
Simon Glass7cf5fe02019-05-02 10:52:12 -0600121 jump_to_spl(spl_image->entry_point);
Simon Glass39c6f9b2019-09-25 08:11:38 -0600122 hang();
Simon Glass7cf5fe02019-05-02 10:52:12 -0600123}
124
125void spl_board_init(void)
126{
127 preloader_console_init();
128}
Simon Glass7b8a5582019-10-20 21:37:50 -0600129
130#if !CONFIG_IS_ENABLED(PCI)
131/*
132 * This is a fake PCI bus for TPL when it doesn't have proper PCI. It is enough
133 * to bind the devices on the PCI bus, some of which have early-regs properties
134 * providing fixed BARs. Individual drivers program these BARs themselves so
135 * that they can access the devices. The BARs are allocated statically in the
136 * device tree.
137 *
138 * Once SPL is running it enables PCI properly, but does not auto-assign BARs
139 * for devices, so the TPL BARs continue to be used. Once U-Boot starts it does
140 * the auto allocation (after relocation).
141 */
Simon Glasse1bafd52020-12-23 08:11:32 -0700142#if !CONFIG_IS_ENABLED(OF_PLATDATA)
Simon Glass7b8a5582019-10-20 21:37:50 -0600143static const struct udevice_id tpl_fake_pci_ids[] = {
144 { .compatible = "pci-x86" },
145 { }
146};
Simon Glasse1bafd52020-12-23 08:11:32 -0700147#endif
Simon Glass7b8a5582019-10-20 21:37:50 -0600148
149U_BOOT_DRIVER(pci_x86) = {
150 .name = "pci_x86",
151 .id = UCLASS_SIMPLE_BUS,
Simon Glasse1bafd52020-12-23 08:11:32 -0700152 .of_match = of_match_ptr(tpl_fake_pci_ids),
Simon Glassf7ffa922021-03-15 17:25:48 +1300153 DM_PHASE(tpl)
Simon Glass7b8a5582019-10-20 21:37:50 -0600154};
155#endif