Simon Glass | 582ba6e | 2019-12-06 21:42:58 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Special driver to handle of-platdata |
| 4 | * |
| 5 | * Copyright 2019 Google LLC |
| 6 | * |
| 7 | * Some code from coreboot lpss.c |
| 8 | */ |
| 9 | |
| 10 | #include <common.h> |
| 11 | #include <dm.h> |
| 12 | #include <dt-structs.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 13 | #include <malloc.h> |
Simon Glass | 582ba6e | 2019-12-06 21:42:58 -0700 | [diff] [blame] | 14 | #include <ns16550.h> |
| 15 | #include <spl.h> |
| 16 | #include <asm/io.h> |
| 17 | #include <asm/pci.h> |
| 18 | #include <asm/lpss.h> |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 19 | #include <dm/device-internal.h> |
Simon Glass | 298530a | 2020-12-19 10:40:05 -0700 | [diff] [blame] | 20 | #include <asm/arch/uart.h> |
Simon Glass | 582ba6e | 2019-12-06 21:42:58 -0700 | [diff] [blame] | 21 | |
| 22 | /* Low-power Subsystem (LPSS) clock register */ |
| 23 | enum { |
| 24 | LPSS_CLOCK_CTL_REG = 0x200, |
| 25 | LPSS_CNT_CLOCK_EN = 1, |
| 26 | LPSS_CNT_CLK_UPDATE = 1U << 31, |
| 27 | LPSS_CLOCK_DIV_N_SHIFT = 16, |
| 28 | LPSS_CLOCK_DIV_N_MASK = 0x7fff << LPSS_CLOCK_DIV_N_SHIFT, |
| 29 | LPSS_CLOCK_DIV_M_SHIFT = 1, |
| 30 | LPSS_CLOCK_DIV_M_MASK = 0x7fff << LPSS_CLOCK_DIV_M_SHIFT, |
| 31 | |
| 32 | /* These set the UART input clock speed */ |
| 33 | LPSS_UART_CLK_M_VAL = 0x25a, |
| 34 | LPSS_UART_CLK_N_VAL = 0x7fff, |
| 35 | }; |
| 36 | |
| 37 | static void lpss_clk_update(void *regs, u32 clk_m_val, u32 clk_n_val) |
| 38 | { |
| 39 | u32 clk_sel; |
| 40 | |
| 41 | clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | |
| 42 | clk_m_val << LPSS_CLOCK_DIV_M_SHIFT; |
| 43 | clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; |
| 44 | |
| 45 | writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); |
| 46 | } |
| 47 | |
| 48 | static void uart_lpss_init(void *regs) |
| 49 | { |
| 50 | /* Take UART out of reset */ |
| 51 | lpss_reset_release(regs); |
| 52 | |
| 53 | /* Set M and N divisor inputs and enable clock */ |
| 54 | lpss_clk_update(regs, LPSS_UART_CLK_M_VAL, LPSS_UART_CLK_N_VAL); |
| 55 | } |
| 56 | |
| 57 | void apl_uart_init(pci_dev_t bdf, ulong base) |
| 58 | { |
| 59 | /* Set UART base address */ |
| 60 | pci_x86_write_config(bdf, PCI_BASE_ADDRESS_0, base, PCI_SIZE_32); |
| 61 | |
| 62 | /* Enable memory access and bus master */ |
| 63 | pci_x86_write_config(bdf, PCI_COMMAND, PCI_COMMAND_MEMORY | |
| 64 | PCI_COMMAND_MASTER, PCI_SIZE_32); |
| 65 | |
| 66 | uart_lpss_init((void *)base); |
| 67 | } |
| 68 | |
| 69 | /* |
| 70 | * This driver uses its own compatible string but almost everything else from |
| 71 | * the standard ns16550 driver. This allows us to provide an of-platdata |
| 72 | * implementation, since the platdata produced by of-platdata does not match |
Simon Glass | 298530a | 2020-12-19 10:40:05 -0700 | [diff] [blame] | 73 | * struct apl_ns16550_plat. |
Simon Glass | 582ba6e | 2019-12-06 21:42:58 -0700 | [diff] [blame] | 74 | * |
| 75 | * When running with of-platdata (generally TPL), the platdata is converted to |
| 76 | * something that ns16550 expects. When running withoutof-platdata (SPL, U-Boot |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 77 | * proper), we use ns16550's of_to_plat routine. |
Simon Glass | 582ba6e | 2019-12-06 21:42:58 -0700 | [diff] [blame] | 78 | */ |
| 79 | |
| 80 | static int apl_ns16550_probe(struct udevice *dev) |
| 81 | { |
Simon Glass | 298530a | 2020-12-19 10:40:05 -0700 | [diff] [blame] | 82 | struct apl_ns16550_plat *plat = dev_get_plat(dev); |
Simon Glass | 582ba6e | 2019-12-06 21:42:58 -0700 | [diff] [blame] | 83 | |
| 84 | if (!CONFIG_IS_ENABLED(PCI)) |
Simon Glass | 298530a | 2020-12-19 10:40:05 -0700 | [diff] [blame] | 85 | apl_uart_init(plat->ns16550.bdf, plat->ns16550.base); |
Simon Glass | 582ba6e | 2019-12-06 21:42:58 -0700 | [diff] [blame] | 86 | |
| 87 | return ns16550_serial_probe(dev); |
| 88 | } |
| 89 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 90 | static int apl_ns16550_of_to_plat(struct udevice *dev) |
Simon Glass | 582ba6e | 2019-12-06 21:42:58 -0700 | [diff] [blame] | 91 | { |
| 92 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
Simon Glass | 298530a | 2020-12-19 10:40:05 -0700 | [diff] [blame] | 93 | struct dtd_intel_apl_ns16550 *dtplat; |
| 94 | struct apl_ns16550_plat *plat = dev_get_plat(dev); |
| 95 | struct ns16550_plat ns; |
Simon Glass | 582ba6e | 2019-12-06 21:42:58 -0700 | [diff] [blame] | 96 | |
| 97 | /* |
Simon Glass | 298530a | 2020-12-19 10:40:05 -0700 | [diff] [blame] | 98 | * The device's plat uses struct apl_ns16550_plat which starts with the |
| 99 | * dtd struct, but the ns16550 driver expects it to be struct ns16550. |
| 100 | * Set up what that driver expects. Note that this means that the values |
| 101 | * cannot be read in this driver when using of-platdata. |
| 102 | * |
| 103 | * TODO(sjg@chromium.org): Consider having a separate plat pointer for |
| 104 | * of-platdata so that it is not necessary to overwrite this. |
Simon Glass | 582ba6e | 2019-12-06 21:42:58 -0700 | [diff] [blame] | 105 | */ |
Simon Glass | 298530a | 2020-12-19 10:40:05 -0700 | [diff] [blame] | 106 | dtplat = &plat->dtplat; |
| 107 | ns.base = dtplat->early_regs[0]; |
| 108 | ns.reg_width = 1; |
| 109 | ns.reg_shift = dtplat->reg_shift; |
| 110 | ns.reg_offset = 0; |
| 111 | ns.clock = dtplat->clock_frequency; |
| 112 | ns.fcr = UART_FCR_DEFVAL; |
| 113 | ns.bdf = pci_ofplat_get_devfn(dtplat->reg[0]); |
| 114 | memcpy(plat, &ns, sizeof(ns)); |
Simon Glass | 582ba6e | 2019-12-06 21:42:58 -0700 | [diff] [blame] | 115 | #else |
| 116 | int ret; |
| 117 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 118 | ret = ns16550_serial_of_to_plat(dev); |
Simon Glass | 582ba6e | 2019-12-06 21:42:58 -0700 | [diff] [blame] | 119 | if (ret) |
| 120 | return ret; |
| 121 | #endif /* OF_PLATDATA */ |
| 122 | |
| 123 | return 0; |
| 124 | } |
| 125 | |
Simon Glass | ec8ae8a | 2020-12-23 08:11:30 -0700 | [diff] [blame] | 126 | #if !CONFIG_IS_ENABLED(OF_PLATDATA) |
Simon Glass | 582ba6e | 2019-12-06 21:42:58 -0700 | [diff] [blame] | 127 | static const struct udevice_id apl_ns16550_serial_ids[] = { |
| 128 | { .compatible = "intel,apl-ns16550" }, |
| 129 | { }, |
| 130 | }; |
Simon Glass | ec8ae8a | 2020-12-23 08:11:30 -0700 | [diff] [blame] | 131 | #endif |
Simon Glass | 582ba6e | 2019-12-06 21:42:58 -0700 | [diff] [blame] | 132 | |
Simon Glass | a055da8 | 2020-10-05 05:27:01 -0600 | [diff] [blame] | 133 | U_BOOT_DRIVER(intel_apl_ns16550) = { |
Simon Glass | 582ba6e | 2019-12-06 21:42:58 -0700 | [diff] [blame] | 134 | .name = "intel_apl_ns16550", |
| 135 | .id = UCLASS_SERIAL, |
Simon Glass | ec8ae8a | 2020-12-23 08:11:30 -0700 | [diff] [blame] | 136 | .of_match = of_match_ptr(apl_ns16550_serial_ids), |
Simon Glass | 298530a | 2020-12-19 10:40:05 -0700 | [diff] [blame] | 137 | .plat_auto = sizeof(struct apl_ns16550_plat), |
Simon Glass | 119e7ef | 2020-12-22 19:30:18 -0700 | [diff] [blame] | 138 | .priv_auto = sizeof(struct ns16550), |
Simon Glass | 582ba6e | 2019-12-06 21:42:58 -0700 | [diff] [blame] | 139 | .ops = &ns16550_serial_ops, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 140 | .of_to_plat = apl_ns16550_of_to_plat, |
Simon Glass | 582ba6e | 2019-12-06 21:42:58 -0700 | [diff] [blame] | 141 | .probe = apl_ns16550_probe, |
| 142 | }; |