| Kumar Gala | fe13711 | 2011-01-19 03:05:26 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License as |
| 6 | * published by the Free Software Foundation; either version 2 of |
| 7 | * the License, or (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 17 | * MA 02111-1307 USA |
| 18 | * |
| 19 | */ |
| 20 | |
| 21 | #ifndef _ASM_MPC85xx_CONFIG_H_ |
| 22 | #define _ASM_MPC85xx_CONFIG_H_ |
| 23 | |
| 24 | /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ |
| 25 | |
| 26 | /* Number of TLB CAM entries we have on FSL Book-E chips */ |
| 27 | #if defined(CONFIG_E500MC) |
| 28 | #define CONFIG_SYS_NUM_TLBCAMS 64 |
| 29 | #elif defined(CONFIG_E500) |
| 30 | #define CONFIG_SYS_NUM_TLBCAMS 16 |
| 31 | #endif |
| 32 | |
| 33 | #if defined(CONFIG_MPC8536) |
| 34 | #define CONFIG_MAX_CPUS 1 |
| 35 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
| 36 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
| 37 | |
| 38 | #elif defined(CONFIG_MPC8540) |
| 39 | #define CONFIG_MAX_CPUS 1 |
| 40 | #define CONFIG_SYS_FSL_NUM_LAWS 8 |
| 41 | |
| 42 | #elif defined(CONFIG_MPC8541) |
| 43 | #define CONFIG_MAX_CPUS 1 |
| 44 | #define CONFIG_SYS_FSL_NUM_LAWS 8 |
| 45 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
| 46 | |
| 47 | #elif defined(CONFIG_MPC8544) |
| 48 | #define CONFIG_MAX_CPUS 1 |
| 49 | #define CONFIG_SYS_FSL_NUM_LAWS 10 |
| 50 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
| 51 | |
| 52 | #elif defined(CONFIG_MPC8548) |
| 53 | #define CONFIG_MAX_CPUS 1 |
| 54 | #define CONFIG_SYS_FSL_NUM_LAWS 10 |
| 55 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
| 56 | |
| 57 | #elif defined(CONFIG_MPC8555) |
| 58 | #define CONFIG_MAX_CPUS 1 |
| 59 | #define CONFIG_SYS_FSL_NUM_LAWS 8 |
| 60 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
| 61 | |
| 62 | #elif defined(CONFIG_MPC8560) |
| 63 | #define CONFIG_MAX_CPUS 1 |
| 64 | #define CONFIG_SYS_FSL_NUM_LAWS 8 |
| 65 | |
| 66 | #elif defined(CONFIG_MPC8568) |
| 67 | #define CONFIG_MAX_CPUS 1 |
| 68 | #define CONFIG_SYS_FSL_NUM_LAWS 10 |
| 69 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
| 70 | |
| 71 | #elif defined(CONFIG_MPC8569) |
| 72 | #define CONFIG_MAX_CPUS 1 |
| 73 | #define CONFIG_SYS_FSL_NUM_LAWS 10 |
| 74 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
| 75 | |
| 76 | #elif defined(CONFIG_MPC8572) |
| 77 | #define CONFIG_MAX_CPUS 2 |
| 78 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
| 79 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
| 80 | |
| 81 | #elif defined(CONFIG_P1010) |
| 82 | #define CONFIG_MAX_CPUS 1 |
| 83 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
| 84 | #define CONFIG_TSECV2 |
| 85 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 |
| 86 | |
| 87 | #elif defined(CONFIG_P1011) |
| 88 | #define CONFIG_MAX_CPUS 1 |
| 89 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
| 90 | #define CONFIG_TSECV2 |
| 91 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
| 92 | |
| 93 | #elif defined(CONFIG_P1012) |
| 94 | #define CONFIG_MAX_CPUS 1 |
| 95 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
| 96 | #define CONFIG_TSECV2 |
| 97 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
| 98 | |
| 99 | #elif defined(CONFIG_P1013) |
| 100 | #define CONFIG_MAX_CPUS 1 |
| 101 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
| 102 | #define CONFIG_TSECV2 |
| 103 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
| 104 | |
| 105 | #elif defined(CONFIG_P1014) |
| 106 | #define CONFIG_MAX_CPUS 1 |
| 107 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
| 108 | #define CONFIG_TSECV2 |
| 109 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 |
| 110 | |
| 111 | #elif defined(CONFIG_P1020) |
| 112 | #define CONFIG_MAX_CPUS 2 |
| 113 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
| 114 | #define CONFIG_TSECV2 |
| 115 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
| 116 | |
| 117 | #elif defined(CONFIG_P1021) |
| 118 | #define CONFIG_MAX_CPUS 2 |
| 119 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
| 120 | #define CONFIG_TSECV2 |
| 121 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
| 122 | |
| 123 | #elif defined(CONFIG_P1022) |
| 124 | #define CONFIG_MAX_CPUS 2 |
| 125 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
| 126 | #define CONFIG_TSECV2 |
| 127 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
| 128 | |
| 129 | #elif defined(CONFIG_P2010) |
| 130 | #define CONFIG_MAX_CPUS 1 |
| 131 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
| 132 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
| 133 | |
| 134 | #elif defined(CONFIG_P2020) |
| 135 | #define CONFIG_MAX_CPUS 2 |
| 136 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
| 137 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
| 138 | |
| 139 | #elif defined(CONFIG_PPC_P2040) |
| 140 | #define CONFIG_MAX_CPUS 4 |
| 141 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
| 142 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 |
| 143 | |
| 144 | #elif defined(CONFIG_PPC_P3041) |
| 145 | #define CONFIG_MAX_CPUS 4 |
| 146 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
| 147 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 |
| 148 | |
| 149 | #elif defined(CONFIG_PPC_P4040) |
| 150 | #define CONFIG_MAX_CPUS 4 |
| 151 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
| 152 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 |
| 153 | |
| 154 | #elif defined(CONFIG_PPC_P4080) |
| 155 | #define CONFIG_MAX_CPUS 8 |
| 156 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
| 157 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 |
| 158 | #define CONFIG_SYS_NUM_FMAN 2 |
| 159 | #define CONFIG_SYS_NUM_FM1_DTSEC 4 |
| 160 | #define CONFIG_SYS_NUM_FM2_DTSEC 4 |
| 161 | #define CONFIG_SYS_NUM_FM1_10GEC 1 |
| 162 | #define CONFIG_SYS_NUM_FM2_10GEC 1 |
| 163 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
| 164 | #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 |
| 165 | #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 |
| 166 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
| 167 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
| 168 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 |
| 169 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC136 |
| 170 | #define CONFIG_SYS_P4080_ERRATUM_CPU22 |
| 171 | #define CONFIG_SYS_P4080_ERRATUM_SERDES8 |
| 172 | |
| 173 | #elif defined(CONFIG_PPC_P5010) |
| 174 | #define CONFIG_MAX_CPUS 1 |
| 175 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
| 176 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 |
| 177 | |
| 178 | #elif defined(CONFIG_PPC_P5020) |
| 179 | #define CONFIG_MAX_CPUS 2 |
| 180 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
| 181 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 |
| 182 | |
| 183 | #else |
| 184 | #error Processor type not defined for this platform |
| 185 | #endif |
| 186 | |
| 187 | #endif /* _ASM_MPC85xx_CONFIG_H_ */ |