blob: 9e00eef1f4b69f59df8c198db1f02e4b6de07422 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenk12490652004-04-18 21:13:41 +00002/*
Michal Simek922ce202007-03-11 13:48:24 +01003 * (C) Copyright 2007 Michal Simek
wdenk12490652004-04-18 21:13:41 +00004 * (C) Copyright 2004 Atmark Techno, Inc.
5 *
Michal Simek922ce202007-03-11 13:48:24 +01006 * Michal SIMEK <monstr@monstr.eu>
wdenk12490652004-04-18 21:13:41 +00007 * Yasushi SHOJI <yashi@atmark-techno.com>
wdenk12490652004-04-18 21:13:41 +00008 */
9
Wolfgang Denk0191e472010-10-26 14:34:52 +020010#include <asm-offsets.h>
wdenk12490652004-04-18 21:13:41 +000011#include <config.h>
12
13 .text
14 .global _start
15_start:
Michal Simek922ce202007-03-11 13:48:24 +010016 mts rmsr, r0 /* disable cache */
Michal Simek26acb3e2014-01-21 07:30:37 +010017
Ovidiu Panait76e51132021-11-30 18:33:49 +020018 addi r8, r0, _end
Michal Simeka5e9d6e2014-11-04 13:30:14 +010019 mts rslr, r8
Ovidiu Panaite6dbb8b2020-09-24 11:54:37 +030020
Michal Simek26acb3e2014-01-21 07:30:37 +010021#if defined(CONFIG_SPL_BUILD)
22 addi r1, r0, CONFIG_SPL_STACK_ADDR
Michal Simek9ea67442015-01-30 15:46:43 +010023#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020024 addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
Michal Simek9ea67442015-01-30 15:46:43 +010025#endif
Ovidiu Panaite6dbb8b2020-09-24 11:54:37 +030026
Michal Simek1f0c40c2007-03-26 01:39:07 +020027 addi r1, r1, -4 /* Decrement SP to top of memory */
Michal Simekead124a2010-08-12 11:47:11 +020028
Ovidiu Panaite6dbb8b2020-09-24 11:54:37 +030029 /* Call board_init_f_alloc_reserve with the current stack pointer as
30 * parameter. */
31 add r5, r0, r1
Michal Simek8f57aec2022-06-24 14:14:59 +020032 brlid r15, board_init_f_alloc_reserve
Ovidiu Panaite6dbb8b2020-09-24 11:54:37 +030033 nop
34
35 /* board_init_f_alloc_reserve returns a pointer to the allocated area
36 * in r3. Set the new stack pointer below this area. */
37 add r1, r0, r3
38 mts rshr, r1
39 addi r1, r1, -4
40
41 /* Call board_init_f_init_reserve with the address returned by
42 * board_init_f_alloc_reserve as parameter. */
43 add r5, r0, r3
Michal Simek8f57aec2022-06-24 14:14:59 +020044 brlid r15, board_init_f_init_reserve
Ovidiu Panaite6dbb8b2020-09-24 11:54:37 +030045 nop
46
47#if !defined(CONFIG_SPL_BUILD)
Ovidiu Panait98558352020-09-24 11:54:36 +030048 /* Setup vectors with pre-relocation symbols */
49 or r5, r0, r0
Michal Simek8f57aec2022-06-24 14:14:59 +020050 brlid r15, __setup_exceptions
Ovidiu Panait98558352020-09-24 11:54:36 +030051 nop
Ovidiu Panaite6dbb8b2020-09-24 11:54:37 +030052#endif
Ovidiu Panait98558352020-09-24 11:54:36 +030053
54 /* Flush cache before enable cache */
55 addik r5, r0, 0
56 addik r6, r0, XILINX_DCACHE_BYTE_SIZE
Michal Simek8f57aec2022-06-24 14:14:59 +020057 brlid r15, flush_cache
Ovidiu Panait98558352020-09-24 11:54:36 +030058 nop
59
60 /* enable instruction and data cache */
61 mfs r12, rmsr
62 ori r12, r12, 0x1a0
63 mts rmsr, r12
64
Ovidiu Panait98558352020-09-24 11:54:36 +030065clear_bss:
66 /* clear BSS segments */
67 addi r5, r0, __bss_start
68 addi r4, r0, __bss_end
69 cmp r6, r5, r4
70 beqi r6, 3f
712:
72 swi r0, r5, 0 /* write zero to loc */
73 addi r5, r5, 4 /* increment to next loc */
74 cmp r6, r5, r4 /* check if we have reach the end */
75 bnei r6, 2b
763: /* jumping to board_init */
77#ifdef CONFIG_DEBUG_UART
Michal Simek8f57aec2022-06-24 14:14:59 +020078 brlid r15, debug_uart_init
Ovidiu Panait98558352020-09-24 11:54:36 +030079 nop
80#endif
81#ifndef CONFIG_SPL_BUILD
82 or r5, r0, r0 /* flags - empty */
Michal Simek8f57aec2022-06-24 14:14:59 +020083 bri board_init_f
Ovidiu Panait98558352020-09-24 11:54:36 +030084#else
Michal Simek8f57aec2022-06-24 14:14:59 +020085 bri board_init_r
Ovidiu Panait98558352020-09-24 11:54:36 +030086#endif
871: bri 1b
88
Ovidiu Panait98558352020-09-24 11:54:36 +030089#ifndef CONFIG_SPL_BUILD
90 .text
91 .ent __setup_exceptions
92 .align 2
93/*
94 * Set up reset, interrupt, user exception and hardware exception vectors.
95 *
96 * Parameters:
97 * r5 - relocation offset (zero when setting up vectors before
98 * relocation, and gd->reloc_off when setting up vectors after
99 * relocation)
100 * - the relocation offset is added to the _exception_handler,
101 * _interrupt_handler and _hw_exception_handler symbols to reflect the
102 * post-relocation memory addresses
103 *
104 * Reserve registers:
105 * r10: Stores little/big endian offset for vectors
106 * r2: Stores imm opcode
107 * r3: Stores brai opcode
Ovidiu Panaite165fa52021-11-30 18:33:56 +0200108 * r4: Stores the vector base address
Ovidiu Panait98558352020-09-24 11:54:36 +0300109 */
110__setup_exceptions:
Ovidiu Panaite165fa52021-11-30 18:33:56 +0200111 addik r1, r1, -32
Ovidiu Panait98558352020-09-24 11:54:36 +0300112 swi r2, r1, 4
113 swi r3, r1, 8
Ovidiu Panaite165fa52021-11-30 18:33:56 +0200114 swi r4, r1, 12
115 swi r6, r1, 16
116 swi r7, r1, 20
117 swi r8, r1, 24
118 swi r10, r1, 28
Ovidiu Panait98558352020-09-24 11:54:36 +0300119
Michal Simekead124a2010-08-12 11:47:11 +0200120 /* Find-out if u-boot is running on BIG/LITTLE endian platform
121 * There are some steps which is necessary to keep in mind:
122 * 1. Setup offset value to r6
123 * 2. Store word offset value to address 0x0
124 * 3. Load just byte from address 0x0
125 * 4a) LITTLE endian - r10 contains 0x2 because it is the smallest
126 * value that's why is on address 0x0
127 * 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
128 */
129 addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
Ovidiu Panaitff759b32021-11-30 18:33:52 +0200130 sw r6, r1, r0
131 lbu r10, r1, r0
Michal Simekead124a2010-08-12 11:47:11 +0200132
Michal Simek4a30db92011-07-21 10:47:21 +0200133 /* add opcode instruction for 32bit jump - 2 instruction imm & brai */
134 addi r2, r0, 0xb0000000 /* hex b000 opcode imm */
135 addi r3, r0, 0xb8080000 /* hew b808 opcode brai */
wdenk12490652004-04-18 21:13:41 +0000136
Ovidiu Panaite165fa52021-11-30 18:33:56 +0200137 /* Store the vector base address in r4 */
138 addi r4, r0, CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR
139
Michal Simek922ce202007-03-11 13:48:24 +0100140 /* reset address */
Ovidiu Panaite165fa52021-11-30 18:33:56 +0200141 swi r2, r4, 0x0 /* reset address - imm opcode */
142 swi r3, r4, 0x4 /* reset address - brai opcode */
Michal Simek4a30db92011-07-21 10:47:21 +0200143
Ovidiu Panaitc7c11c82021-11-30 18:33:53 +0200144 addik r6, r0, CONFIG_SYS_TEXT_BASE
Michal Simek922ce202007-03-11 13:48:24 +0100145 sw r6, r1, r0
Michal Simek8daf0c32011-08-30 15:22:24 +0200146 lhu r7, r1, r10
147 rsubi r8, r10, 0x2
Ovidiu Panaite165fa52021-11-30 18:33:56 +0200148 sh r7, r4, r8
Michal Simek8daf0c32011-08-30 15:22:24 +0200149 rsubi r8, r10, 0x6
Ovidiu Panaite165fa52021-11-30 18:33:56 +0200150 sh r6, r4, r8
Michal Simek922ce202007-03-11 13:48:24 +0100151
Ovidiu Panait39415f72021-11-30 18:33:54 +0200152#if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USR_EXCEP)
Michal Simek922ce202007-03-11 13:48:24 +0100153 /* user_vector_exception */
Ovidiu Panaite165fa52021-11-30 18:33:56 +0200154 swi r2, r4, 0x8 /* user vector exception - imm opcode */
155 swi r3, r4, 0xC /* user vector exception - brai opcode */
Michal Simek4a30db92011-07-21 10:47:21 +0200156
Ovidiu Panait98558352020-09-24 11:54:36 +0300157 addik r6, r5, _exception_handler
Michal Simek922ce202007-03-11 13:48:24 +0100158 sw r6, r1, r0
Michal Simekead124a2010-08-12 11:47:11 +0200159 /*
160 * BIG ENDIAN memory map for user exception
161 * 0x8: 0xB000XXXX
162 * 0xC: 0xB808XXXX
163 *
164 * then it is necessary to count address for storing the most significant
Wolfgang Denk1136f692010-10-27 22:48:30 +0200165 * 16bits from _exception_handler address and copy it to
Michal Simekead124a2010-08-12 11:47:11 +0200166 * 0xa address. Big endian use offset in r10=0 that's why is it just
167 * 0xa address. The same is done for the least significant 16 bits
168 * for 0xe address.
169 *
170 * LITTLE ENDIAN memory map for user exception
171 * 0x8: 0xXXXX00B0
172 * 0xC: 0xXXXX08B8
173 *
174 * Offset is for little endian setup to 0x2. rsubi instruction decrease
175 * address value to ensure that points to proper place which is
176 * 0x8 for the most significant 16 bits and
177 * 0xC for the least significant 16 bits
178 */
179 lhu r7, r1, r10
180 rsubi r8, r10, 0xa
Ovidiu Panaite165fa52021-11-30 18:33:56 +0200181 sh r7, r4, r8
Michal Simekead124a2010-08-12 11:47:11 +0200182 rsubi r8, r10, 0xe
Ovidiu Panaite165fa52021-11-30 18:33:56 +0200183 sh r6, r4, r8
Michal Simek922ce202007-03-11 13:48:24 +0100184#endif
185
Michal Simek922ce202007-03-11 13:48:24 +0100186 /* interrupt_handler */
Ovidiu Panaite165fa52021-11-30 18:33:56 +0200187 swi r2, r4, 0x10 /* interrupt - imm opcode */
188 swi r3, r4, 0x14 /* interrupt - brai opcode */
Michal Simek4a30db92011-07-21 10:47:21 +0200189
Ovidiu Panait98558352020-09-24 11:54:36 +0300190 addik r6, r5, _interrupt_handler
Michal Simek922ce202007-03-11 13:48:24 +0100191 sw r6, r1, r0
Michal Simekead124a2010-08-12 11:47:11 +0200192 lhu r7, r1, r10
193 rsubi r8, r10, 0x12
Ovidiu Panaite165fa52021-11-30 18:33:56 +0200194 sh r7, r4, r8
Michal Simekead124a2010-08-12 11:47:11 +0200195 rsubi r8, r10, 0x16
Ovidiu Panaite165fa52021-11-30 18:33:56 +0200196 sh r6, r4, r8
wdenk12490652004-04-18 21:13:41 +0000197
Michal Simek922ce202007-03-11 13:48:24 +0100198 /* hardware exception */
Ovidiu Panaite165fa52021-11-30 18:33:56 +0200199 swi r2, r4, 0x20 /* hardware exception - imm opcode */
200 swi r3, r4, 0x24 /* hardware exception - brai opcode */
Michal Simek4a30db92011-07-21 10:47:21 +0200201
Ovidiu Panait98558352020-09-24 11:54:36 +0300202 addik r6, r5, _hw_exception_handler
Michal Simek922ce202007-03-11 13:48:24 +0100203 sw r6, r1, r0
Michal Simekead124a2010-08-12 11:47:11 +0200204 lhu r7, r1, r10
205 rsubi r8, r10, 0x22
Ovidiu Panaite165fa52021-11-30 18:33:56 +0200206 sh r7, r4, r8
Michal Simekead124a2010-08-12 11:47:11 +0200207 rsubi r8, r10, 0x26
Ovidiu Panaite165fa52021-11-30 18:33:56 +0200208 sh r6, r4, r8
Michal Simek922ce202007-03-11 13:48:24 +0100209
Ovidiu Panaite165fa52021-11-30 18:33:56 +0200210 lwi r10, r1, 28
211 lwi r8, r1, 24
212 lwi r7, r1, 20
213 lwi r6, r1, 16
214 lwi r4, r1, 12
Ovidiu Panait98558352020-09-24 11:54:36 +0300215 lwi r3, r1, 8
216 lwi r2, r1, 4
Ovidiu Panaite165fa52021-11-30 18:33:56 +0200217 addik r1, r1, 32
Michal Simeke3aa3d52012-09-25 10:13:35 +0200218
Ovidiu Panait98558352020-09-24 11:54:36 +0300219 rtsd r15, 8
220 or r0, r0, r0
221 .end __setup_exceptions
Michal Simeka79d6582015-01-30 15:45:02 +0100222
Michal Simek04ae75f2007-04-21 21:02:40 +0200223/*
224 * Read 16bit little endian
225 */
226 .text
227 .global in16
228 .ent in16
229 .align 2
230in16: lhu r3, r0, r5
231 bslli r4, r3, 8
232 bsrli r3, r3, 8
233 andi r4, r4, 0xffff
234 or r3, r3, r4
235 rtsd r15, 8
236 sext16 r3, r3
237 .end in16
238
239/*
240 * Write 16bit little endian
241 * first parameter(r5) - address, second(r6) - short value
242 */
243 .text
244 .global out16
245 .ent out16
246 .align 2
247out16: bslli r3, r6, 8
248 bsrli r6, r6, 8
249 andi r3, r3, 0xffff
250 or r3, r3, r6
251 sh r3, r0, r5
252 rtsd r15, 8
253 or r0, r0, r0
254 .end out16
Michal Simek65e915c2014-05-08 16:08:44 +0200255
256/*
257 * Relocate u-boot
258 */
259 .text
260 .global relocate_code
261 .ent relocate_code
262 .align 2
263relocate_code:
264 /*
265 * r5 - start_addr_sp
266 * r6 - new_gd
267 * r7 - reloc_addr
268 */
269 addi r1, r5, 0 /* Start to use new SP */
270 addi r31, r6, 0 /* Start to use new GD */
271
272 add r23, r0, r7 /* Move reloc addr to r23 */
273 /* Relocate text and data - r12 temp value */
274 addi r21, r0, _start
Ovidiu Panait76e51132021-11-30 18:33:49 +0200275 addi r22, r0, _end - 4 /* Include BSS too */
Michal Simeka9228f62015-01-27 15:10:37 +0100276
277 rsub r6, r21, r22
278 or r5, r0, r0
2791: lw r12, r21, r5 /* Load u-boot data */
280 sw r12, r23, r5 /* Write zero to loc */
281 cmp r12, r5, r6 /* Check if we have reach the end */
Michal Simek65e915c2014-05-08 16:08:44 +0200282 bneid r12, 1b
Michal Simeka9228f62015-01-27 15:10:37 +0100283 addi r5, r5, 4 /* Increment to next loc - relocate code */
Michal Simek65e915c2014-05-08 16:08:44 +0200284
Michal Simek55df7da2019-10-21 12:20:16 +0200285 /* R23 points to the base address. */
Michal Simek65e915c2014-05-08 16:08:44 +0200286 add r23, r0, r7 /* Move reloc addr to r23 */
287 addi r24, r0, CONFIG_SYS_TEXT_BASE /* Get reloc offset */
288 rsub r23, r24, r23 /* keep - this is already here gd->reloc_off */
289
Ovidiu Panait98558352020-09-24 11:54:36 +0300290 /* Setup vectors with post-relocation symbols */
291 add r5, r0, r23 /* load gd->reloc_off to r5 */
Michal Simek8f57aec2022-06-24 14:14:59 +0200292 brlid r15, __setup_exceptions
Ovidiu Panait98558352020-09-24 11:54:36 +0300293 nop
Michal Simek65e915c2014-05-08 16:08:44 +0200294
295 /* Check if GOT exist */
296 addik r21, r23, _got_start
297 addik r22, r23, _got_end
298 cmpu r12, r21, r22
299 beqi r12, 2f /* No GOT table - jump over */
300
301 /* Skip last 3 entries plus 1 because of loop boundary below */
302 addik r22, r22, -0x10
303
304 /* Relocate the GOT. */
3053: lw r12, r21, r0 /* Load entry */
306 addk r12, r12, r23 /* Add reloc offset */
307 sw r12, r21, r0 /* Save entry back */
308
309 cmpu r12, r21, r22 /* Check if this cross boundary */
310 bneid r12, 3b
311 addik r21. r21, 4
312
313 /* Update pointer to GOT */
314 mfs r20, rpc
315 addik r20, r20, _GLOBAL_OFFSET_TABLE_ + 8
316 addk r20, r20, r23
317
318 /* Flush caches to ensure consistency */
319 addik r5, r0, 0
320 addik r6, r0, XILINX_DCACHE_BYTE_SIZE
Michal Simek8f57aec2022-06-24 14:14:59 +0200321 brlid r15, flush_cache
Michal Simek65e915c2014-05-08 16:08:44 +0200322 nop
323
3242: addi r5, r31, 0 /* gd is initialized in board_r.c */
325 addi r6, r0, CONFIG_SYS_TEXT_BASE
326 addi r12, r23, board_init_r
327 bra r12 /* Jump to relocated code */
328
329 .end relocate_code
Michal Simek26acb3e2014-01-21 07:30:37 +0100330#endif