Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2002 |
| 4 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 5 | * Marius Groeger <mgroeger@sysgo.de> |
| 6 | * |
| 7 | * (C) Copyright 2002 |
| 8 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 9 | * Alex Zuepke <azu@sysgo.de> |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | /* |
| 13 | * CPU specific code |
| 14 | */ |
| 15 | |
| 16 | #include <common.h> |
| 17 | #include <command.h> |
Simon Glass | 1d91ba7 | 2019-11-14 12:57:37 -0700 | [diff] [blame] | 18 | #include <cpu_func.h> |
Simon Glass | 8f3f761 | 2019-11-14 12:57:42 -0700 | [diff] [blame^] | 19 | #include <irq_func.h> |
Jean-Christophe PLAGNIOL-VILLARD | 9053b5a | 2009-04-05 13:02:43 +0200 | [diff] [blame] | 20 | #include <asm/system.h> |
Albert ARIBAUD | 21505f9 | 2014-04-15 16:13:48 +0200 | [diff] [blame] | 21 | #include <asm/io.h> |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 22 | |
Jean-Christophe PLAGNIOL-VILLARD | e6b5f1b | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 23 | static void cache_flush(void); |
| 24 | |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 25 | int cleanup_before_linux (void) |
| 26 | { |
| 27 | /* |
| 28 | * this function is called just before we call linux |
| 29 | * it prepares the processor for linux |
| 30 | * |
| 31 | * just disable everything that can disturb booting linux |
| 32 | */ |
| 33 | |
Simon Glass | f87959b | 2019-11-14 12:57:40 -0700 | [diff] [blame] | 34 | disable_interrupts(); |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 35 | |
| 36 | /* turn off I-cache */ |
Jean-Christophe PLAGNIOL-VILLARD | e6b5f1b | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 37 | icache_disable(); |
| 38 | dcache_disable(); |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 39 | |
| 40 | /* flush I-cache */ |
Jean-Christophe PLAGNIOL-VILLARD | e6b5f1b | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 41 | cache_flush(); |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 42 | |
| 43 | return (0); |
| 44 | } |
| 45 | |
Jean-Christophe PLAGNIOL-VILLARD | e6b5f1b | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 46 | /* flush I/D-cache */ |
| 47 | static void cache_flush (void) |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 48 | { |
Jean-Christophe PLAGNIOL-VILLARD | e6b5f1b | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 49 | unsigned long i = 0; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 50 | |
Jean-Christophe PLAGNIOL-VILLARD | e6b5f1b | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 51 | asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 52 | } |
Albert ARIBAUD | 21505f9 | 2014-04-15 16:13:48 +0200 | [diff] [blame] | 53 | |
| 54 | #define RST_BASE 0x90030000 |
| 55 | #define RSRR 0x00 |
| 56 | #define RCSR 0x04 |
| 57 | |
| 58 | __attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused))) |
| 59 | { |
| 60 | /* repeat endlessly */ |
| 61 | while (1) { |
| 62 | writel(0, RST_BASE + RCSR); |
| 63 | writel(1, RST_BASE + RSRR); |
| 64 | } |
| 65 | } |