blob: 83243fb1070f8a7279d854638c3fa47ce57926f6 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001# SPDX-License-Identifier: GPL-2.0+
Jean-Christophe PLAGNIOL-VILLARDc0268772008-10-31 12:26:55 +01002#
3# (C) Copyright 2008
4# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Jean-Christophe PLAGNIOL-VILLARDc0268772008-10-31 12:26:55 +01005
Masahiro Yamada5594ce42013-10-17 17:34:57 +09006obj-y += fpga.o
7obj-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
8obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
Siva Durga Prasad Paladugub7398972019-08-05 15:54:59 +05309obj-$(CONFIG_FPGA_VERSALPL) += versalpl.o
Masahiro Yamada5594ce42013-10-17 17:34:57 +090010obj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
11obj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o
Siva Durga Prasad Paladugu460fdce2016-01-13 16:25:37 +053012obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o
Masahiro Yamada5594ce42013-10-17 17:34:57 +090013obj-$(CONFIG_FPGA_XILINX) += xilinx.o
14obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
Jean-Christophe PLAGNIOL-VILLARDc0268772008-10-31 12:26:55 +010015ifdef CONFIG_FPGA_ALTERA
Masahiro Yamada5594ce42013-10-17 17:34:57 +090016obj-y += altera.o
17obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
18obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
Chee Hong Ang14192452020-08-07 11:50:03 +080019obj-$(CONFIG_FPGA_INTEL_SDM_MAILBOX) += intel_sdm_mb.o
Masahiro Yamada5594ce42013-10-17 17:34:57 +090020obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
Stefan Roesed919d722016-02-12 13:48:02 +010021obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
Pavel Machekc7213802014-09-08 14:08:45 +020022obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
Tien Fong Chee31e50f42017-07-26 13:05:38 +080023obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
Tien Fong Chee1d675f32017-07-26 13:05:43 +080024obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
Jean-Christophe PLAGNIOL-VILLARDc0268772008-10-31 12:26:55 +010025endif