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TsiChungLiew8cb946d2008-01-15 14:15:46 -06001/*
2 * Configuation settings for the Freescale MCF5485 FireEngine board.
3 *
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
TsiChungLiew8cb946d2008-01-15 14:15:46 -06008 */
9
10/*
11 * board/config.h - configuration options, board specific
12 */
13
14#ifndef _M5485EVB_H
15#define _M5485EVB_H
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
TsiChungLiew8cb946d2008-01-15 14:15:46 -060021
TsiChungLiew8cb946d2008-01-15 14:15:46 -060022#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020023#define CONFIG_SYS_UART_PORT (0)
TsiChungLiew8cb946d2008-01-15 14:15:46 -060024
Alison Wang8f6d8f32015-02-12 18:33:15 +080025#undef CONFIG_HW_WATCHDOG
TsiChungLiew8cb946d2008-01-15 14:15:46 -060026#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
27
28/* Command line configuration */
TsiChungLiew8cb946d2008-01-15 14:15:46 -060029#define CONFIG_CMD_PCI
TsiChungLiew8cb946d2008-01-15 14:15:46 -060030
31#define CONFIG_SLTTMR
32
33#define CONFIG_FSLDMAFEC
34#ifdef CONFIG_FSLDMAFEC
TsiChungLiew8cb946d2008-01-15 14:15:46 -060035# define CONFIG_MII 1
TsiChung Liewb3162452008-03-30 01:22:13 -050036# define CONFIG_MII_INIT 1
TsiChungLiew8cb946d2008-01-15 14:15:46 -060037# define CONFIG_HAS_ETH1
38
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020039# define CONFIG_SYS_DMA_USE_INTSRAM 1
40# define CONFIG_SYS_DISCOVER_PHY
41# define CONFIG_SYS_RX_ETH_BUFFER 32
42# define CONFIG_SYS_TX_ETH_BUFFER 48
43# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew8cb946d2008-01-15 14:15:46 -060044
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020045# define CONFIG_SYS_FEC0_PINMUX 0
46# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
47# define CONFIG_SYS_FEC1_PINMUX 0
48# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
TsiChungLiew8cb946d2008-01-15 14:15:46 -060049
Wolfgang Denka1be4762008-05-20 16:00:29 +020050# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020051/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
52# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiew8cb946d2008-01-15 14:15:46 -060053# define FECDUPLEX FULL
54# define FECSPEED _100BASET
55# else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020056# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
57# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew8cb946d2008-01-15 14:15:46 -060058# endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020059# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiew8cb946d2008-01-15 14:15:46 -060060
TsiChungLiew8cb946d2008-01-15 14:15:46 -060061# define CONFIG_IPADDR 192.162.1.2
62# define CONFIG_NETMASK 255.255.255.0
63# define CONFIG_SERVERIP 192.162.1.1
64# define CONFIG_GATEWAYIP 192.162.1.1
TsiChungLiew8cb946d2008-01-15 14:15:46 -060065
66#endif
67
68#ifdef CONFIG_CMD_USB
TsiChungLiew8cb946d2008-01-15 14:15:46 -060069# define CONFIG_USB_OHCI_NEW
70# ifndef CONFIG_CMD_PCI
71# define CONFIG_CMD_PCI
72# endif
73/*# define CONFIG_PCI_OHCI*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020074# define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000
75# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
76# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561"
77# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
TsiChungLiew8cb946d2008-01-15 14:15:46 -060078#endif
79
80/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +020081#define CONFIG_SYS_I2C
82#define CONFIG_SYS_I2C_FSL
83#define CONFIG_SYS_FSL_I2C_SPEED 80000
84#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
85#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020086#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
TsiChungLiew8cb946d2008-01-15 14:15:46 -060087
88/* PCI */
89#ifdef CONFIG_CMD_PCI
TsiChung Liew521f97b2008-03-30 01:19:06 -050090#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
TsiChungLiew8cb946d2008-01-15 14:15:46 -060091
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020092#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
93#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
94#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
TsiChungLiew8cb946d2008-01-15 14:15:46 -060095
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020096#define CONFIG_SYS_PCI_IO_BUS 0x71000000
97#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
98#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
TsiChungLiew8cb946d2008-01-15 14:15:46 -060099
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200100#define CONFIG_SYS_PCI_CFG_BUS 0x70000000
101#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
102#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600103#endif
104
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600105#define CONFIG_UDP_CHECKSUM
106
107#define CONFIG_HOSTNAME M548xEVB
108#define CONFIG_EXTRA_ENV_SETTINGS \
109 "netdev=eth0\0" \
110 "loadaddr=10000\0" \
111 "u-boot=u-boot.bin\0" \
112 "load=tftp ${loadaddr) ${u-boot}\0" \
113 "upd=run load; run prog\0" \
114 "prog=prot off bank 1;" \
Jason Jinded4eb42011-08-19 10:10:40 +0800115 "era ff800000 ff83ffff;" \
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600116 "cp.b ${loadaddr} ff800000 ${filesize};"\
117 "save\0" \
118 ""
119
120#define CONFIG_PRAM 512 /* 512 KB */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200121#define CONFIG_SYS_LONGHELP /* undef to save memory */
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600122
123#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200124# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600125#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200126# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600127#endif
128
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
130#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
131#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
132#define CONFIG_SYS_LOAD_ADDR 0x00010000
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600133
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200134#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK
135#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600136
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200137#define CONFIG_SYS_MBAR 0xF0000000
138#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000)
139#define CONFIG_SYS_INTSRAMSZ 0x8000
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600140
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200141/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600142
143/*
144 * Low Level Configuration Settings
145 * (address mappings, register initial values, etc.)
146 * You should know what you are doing if you make changes here.
147 */
148/*-----------------------------------------------------------------------
149 * Definitions for initial stack pointer and data area (in DPRAM)
150 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200151#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200152#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200153#define CONFIG_SYS_INIT_RAM_CTRL 0x21
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200154#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200155#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
156#define CONFIG_SYS_INIT_RAM1_CTRL 0x21
Wolfgang Denk0191e472010-10-26 14:34:52 +0200157#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200158#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600159
160/*-----------------------------------------------------------------------
161 * Start addresses for the final memory configuration
162 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200163 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600164 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200165#define CONFIG_SYS_SDRAM_BASE 0x00000000
166#define CONFIG_SYS_SDRAM_CFG1 0x73711630
167#define CONFIG_SYS_SDRAM_CFG2 0x46770000
168#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000
169#define CONFIG_SYS_SDRAM_EMOD 0x40010000
170#define CONFIG_SYS_SDRAM_MODE 0x018D0000
171#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA
172#ifdef CONFIG_SYS_DRAMSZ1
173# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600174#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200175# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600176#endif
177
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200178#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
179#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600180
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200181#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
182#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600183
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200184#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600185
Jason Jinded4eb42011-08-19 10:10:40 +0800186/* Reserve 256 kB for malloc() */
187#define CONFIG_SYS_MALLOC_LEN (256 << 10)
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600188/*
189 * For booting Linux, the board info and command line data
190 * have to be in the first 8 MB of memory, since this is
191 * the maximum mapped by the Linux kernel during initialization ??
192 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200193#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600194
195/*-----------------------------------------------------------------------
196 * FLASH organization
197 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200198#define CONFIG_SYS_FLASH_CFI
199#ifdef CONFIG_SYS_FLASH_CFI
200# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200201# define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
203# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
204# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
205# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
206#ifdef CONFIG_SYS_NOR1SZ
207# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
208# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
209# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600210#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200211# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
212# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20)
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600213#endif
214#endif
215
216/* Configuration for environment
Jason Jinded4eb42011-08-19 10:10:40 +0800217 * Environment is not embedded in u-boot. First time runing may have env
218 * crc error warning if there is no correct environment on the flash.
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600219 */
Jason Jinded4eb42011-08-19 10:10:40 +0800220#define CONFIG_ENV_OFFSET 0x40000
221#define CONFIG_ENV_SECT_SIZE 0x10000
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600222
223/*-----------------------------------------------------------------------
224 * Cache Configuration
225 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200226#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600227
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600228#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200229 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600230#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200231 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600232#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
233 CF_CACR_IDCM)
234#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
235#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
236 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
237 CF_ACR_EN | CF_ACR_SM_ALL)
238#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \
239 CF_CACR_IEC | CF_CACR_ICINVA)
240#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
241 CF_CACR_DEC | CF_CACR_DDCM_P | \
242 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
243
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600244/*-----------------------------------------------------------------------
245 * Chipselect bank definitions
246 */
247/*
248 * CS0 - NOR Flash 1, 2, 4, or 8MB
249 * CS1 - NOR Flash
250 * CS2 - Available
251 * CS3 - Available
252 * CS4 - Available
253 * CS5 - Available
254 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200255#define CONFIG_SYS_CS0_BASE 0xFF800000
256#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
257#define CONFIG_SYS_CS0_CTRL 0x00101980
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600258
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200259#ifdef CONFIG_SYS_NOR1SZ
260#define CONFIG_SYS_CS1_BASE 0xE0000000
261#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
262#define CONFIG_SYS_CS1_CTRL 0x00101D80
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600263#endif
264
265#endif /* _M5485EVB_H */