blob: 8e8712fecc3733af447245dcb80e53dff2c91523 [file] [log] [blame]
Matt Porter884ea7b2015-05-05 15:00:24 -04001/*
2 * (C) Copyright 2011
3 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
4 *
5 * (C) Copyright 2015
Kamil Lulkodecd33b2015-11-29 11:50:53 +01006 * Kamil Lulko, <kamil.lulko@gmail.com>
Matt Porter884ea7b2015-05-05 15:00:24 -04007 *
8 * Copyright 2015 ATS Advanced Telematics Systems GmbH
9 * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
10 *
11 * SPDX-License-Identifier: GPL-2.0+
12 */
13
14#ifndef _STM32_GPIO_H_
15#define _STM32_GPIO_H_
16
17enum stm32_gpio_port {
18 STM32_GPIO_PORT_A = 0,
19 STM32_GPIO_PORT_B,
20 STM32_GPIO_PORT_C,
21 STM32_GPIO_PORT_D,
22 STM32_GPIO_PORT_E,
23 STM32_GPIO_PORT_F,
24 STM32_GPIO_PORT_G,
25};
26
27enum stm32_gpio_pin {
28 STM32_GPIO_PIN_0 = 0,
29 STM32_GPIO_PIN_1,
30 STM32_GPIO_PIN_2,
31 STM32_GPIO_PIN_3,
32 STM32_GPIO_PIN_4,
33 STM32_GPIO_PIN_5,
34 STM32_GPIO_PIN_6,
35 STM32_GPIO_PIN_7,
36 STM32_GPIO_PIN_8,
37 STM32_GPIO_PIN_9,
38 STM32_GPIO_PIN_10,
39 STM32_GPIO_PIN_11,
40 STM32_GPIO_PIN_12,
41 STM32_GPIO_PIN_13,
42 STM32_GPIO_PIN_14,
43 STM32_GPIO_PIN_15
44};
45
46enum stm32_gpio_icnf {
47 STM32_GPIO_ICNF_AN = 0,
48 STM32_GPIO_ICNF_IN_FLT,
49 STM32_GPIO_ICNF_IN_PUD,
50 STM32_GPIO_ICNF_RSVD
51};
52
53enum stm32_gpio_ocnf {
54 STM32_GPIO_OCNF_GP_PP = 0,
55 STM32_GPIO_OCNF_GP_OD,
56 STM32_GPIO_OCNF_AF_PP,
57 STM32_GPIO_OCNF_AF_OD
58};
59
60enum stm32_gpio_pupd {
61 STM32_GPIO_PUPD_DOWN = 0,
62 STM32_GPIO_PUPD_UP,
63};
64
65enum stm32_gpio_mode {
66 STM32_GPIO_MODE_IN = 0,
67 STM32_GPIO_MODE_OUT_10M,
68 STM32_GPIO_MODE_OUT_2M,
69 STM32_GPIO_MODE_OUT_50M
70};
71
72enum stm32_gpio_af {
73 STM32_GPIO_AF0 = 0,
74 STM32_GPIO_AF1,
75 STM32_GPIO_AF2,
76 STM32_GPIO_AF3,
77 STM32_GPIO_AF4,
78 STM32_GPIO_AF5,
79 STM32_GPIO_AF6,
80 STM32_GPIO_AF7,
81 STM32_GPIO_AF8,
82 STM32_GPIO_AF9,
83 STM32_GPIO_AF10,
84 STM32_GPIO_AF11,
85 STM32_GPIO_AF12,
86 STM32_GPIO_AF13,
87 STM32_GPIO_AF14,
88 STM32_GPIO_AF15
89};
90
91struct stm32_gpio_dsc {
92 enum stm32_gpio_port port;
93 enum stm32_gpio_pin pin;
94};
95
96struct stm32_gpio_ctl {
97 enum stm32_gpio_icnf icnf;
98 enum stm32_gpio_ocnf ocnf;
99 enum stm32_gpio_mode mode;
100 enum stm32_gpio_pupd pupd;
101 enum stm32_gpio_af af;
102};
103
104static inline unsigned stm32_gpio_to_port(unsigned gpio)
105{
106 return gpio / 16;
107}
108
109static inline unsigned stm32_gpio_to_pin(unsigned gpio)
110{
111 return gpio % 16;
112}
113
114int stm32_gpio_config(const struct stm32_gpio_dsc *gpio_dsc,
115 const struct stm32_gpio_ctl *gpio_ctl);
116int stm32_gpout_set(const struct stm32_gpio_dsc *gpio_dsc, int state);
117
118#endif /* _STM32_GPIO_H_ */