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git01.mediatek.com / filogic / uboot / 8d15c694de50b023424691daf376616e9bcb0b57 / . / board / renesas / r7780mp / lowlevel_init.S
blob: bbea621920000bfcaf5b610b3eb5793fa474291b [file] [log] [blame]
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]1/*
2 * Copyright (C) 2007,2008 Nobuhiro Iwamatsu
3 *
4 * u-boot/board/r7780mp/lowlevel_init.S
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#include <config.h>
23#include <version.h>
24#include <asm/processor.h>
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]25#include <asm/macro.h>
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]26
27/*
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]28 * Board specific low level init code, called _very_ early in the
29 * startup sequence. Relocation to SDRAM has not happened yet, no
30 * stack is available, bss section has not been initialised, etc.
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]31 *
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]32 * (Note: As no stack is available, no subroutines can be called...).
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]33 */
34
35 .global lowlevel_init
36
37 .text
38 .align 2
39
40lowlevel_init:
41
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]42 write32 CCR_A, CCR_D /* Address of Cache Control Register */
43 /* Instruction Cache Invalidate */
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]44
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]45 write32 FRQCR_A, FRQCR_D /* Frequency control register */
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]46
47 /* pin_multi_setting */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]48 write32 BBG_PMMR_A, BBG_PMMR_D_PMSR1
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]49
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]50 write32 BBG_PMSR1_A, BBG_PMSR1_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]51
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]52 write32 BBG_PMMR_A, BBG_PMMR_D_PMSR2
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]53
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]54 write32 BBG_PMSR2_A, BBG_PMSR2_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]55
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]56 write32 BBG_PMMR_A, BBG_PMMR_D_PMSR3
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]57
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]58 write32 BBG_PMSR3_A, BBG_PMSR3_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]59
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]60 write32 BBG_PMMR_A, BBG_PMMR_D_PMSR4
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]61
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]62 write32 BBG_PMSR4_A, BBG_PMSR4_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]63
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]64 write32 BBG_PMMR_A, BBG_PMMR_D_PMSRG
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]65
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]66 write32 BBG_PMSRG_A, BBG_PMSRG_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]67
68 /* cpg_setting */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]69 write32 FRQCR_A, FRQCR_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]70
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]71 write32 DLLCSR_A, DLLCSR_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]72
73 nop
74 nop
75 nop
76 nop
77 nop
78 nop
79 nop
80 nop
81 nop
82 nop
83
84 /* wait 200us */
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]85 mov.l REPEAT0_R3, r3
86 mov #0, r2
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]87repeat0:
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]88 add #1, r2
89 cmp/hs r3, r2
90 bf repeat0
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]91 nop
92
93 /* bsc_setting */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]94 write32 MMSELR_A, MMSELR_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]95
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]96 write32 BCR_A, BCR_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]97
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]98 write32 CS0BCR_A, CS0BCR_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]99
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]100 write32 CS1BCR_A, CS1BCR_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]101
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]102 write32 CS2BCR_A, CS2BCR_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]103
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]104 write32 CS4BCR_A, CS4BCR_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]105
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]106 write32 CS5BCR_A, CS5BCR_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]107
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]108 write32 CS6BCR_A, CS6BCR_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]109
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]110 write32 CS0WCR_A, CS0WCR_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]111
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]112 write32 CS1WCR_A, CS1WCR_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]113
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]114 write32 CS2WCR_A, CS2WCR_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]115
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]116 write32 CS4WCR_A, CS4WCR_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]117
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]118 write32 CS5WCR_A, CS5WCR_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]119
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]120 write32 CS6WCR_A, CS6WCR_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]121
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]122 write32 CS5PCR_A, CS5PCR_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]123
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]124 write32 CS6PCR_A, CS6PCR_D
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]125
126 /* ddr_setting */
127 /* wait 200us */
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]128 mov.l REPEAT0_R3, r3
129 mov #0, r2
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]130repeat1:
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]131 add #1, r2
132 cmp/hs r3, r2
133 bf repeat1
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]134 nop
135
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]136 mov.l MIM_U_A, r0
137 mov.l MIM_U_D, r1
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]138 synco
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]139 mov.l r1, @r0
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]140 synco
141
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]142 mov.l MIM_L_A, r0
143 mov.l MIM_L_D0, r1
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]144 synco
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]145 mov.l r1, @r0
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]146 synco
147
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]148 mov.l STR_L_A, r0
149 mov.l STR_L_D, r1
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]150 synco
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]151 mov.l r1, @r0
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]152 synco
153
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]154 mov.l SDR_L_A, r0
155 mov.l SDR_L_D, r1
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]156 synco
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]157 mov.l r1, @r0
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]158 synco
159
160 nop
161 nop
162 nop
163 nop
164
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]165 mov.l SCR_L_A, r0
166 mov.l SCR_L_D0, r1
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]167 synco
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]168 mov.l r1, @r0
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]169 synco
170
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]171 mov.l SCR_L_A, r0
172 mov.l SCR_L_D1, r1
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]173 synco
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]174 mov.l r1, @r0
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]175 synco
176
177 nop
178 nop
179 nop
180
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]181 mov.l EMRS_A, r0
182 mov.l EMRS_D, r1
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]183 synco
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]184 mov.l r1, @r0
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]185 synco
186
187 nop
188 nop
189 nop
190
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]191 mov.l MRS1_A, r0
192 mov.l MRS1_D, r1
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]193 synco
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]194 mov.l r1, @r0
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]195 synco
196
197 nop
198 nop
199 nop
200
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]201 mov.l SCR_L_A, r0
202 mov.l SCR_L_D2, r1
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]203 synco
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]204 mov.l r1, @r0
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]205 synco
206
207 nop
208 nop
209 nop
210
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]211 mov.l SCR_L_A, r0
212 mov.l SCR_L_D3, r1
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]213 synco
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]214 mov.l r1, @r0
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]215 synco
216
217 nop
218 nop
219 nop
220
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]221 mov.l SCR_L_A, r0
222 mov.l SCR_L_D4, r1
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]223 synco
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]224 mov.l r1, @r0
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]225 synco
226
227 nop
228 nop
229 nop
230
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]231 mov.l MRS2_A, r0
232 mov.l MRS2_D, r1
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]233 synco
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]234 mov.l r1, @r0
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]235 synco
236
237 nop
238 nop
239 nop
240
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]241 mov.l SCR_L_A, r0
242 mov.l SCR_L_D5, r1
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]243 synco
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]244 mov.l r1, @r0
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]245 synco
246
247 /* wait 200us */
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]248 mov.l REPEAT0_R1, r3
249 mov #0, r2
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]250repeat2:
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]251 add #1, r2
252 cmp/hs r3, r2
253 bf repeat2
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]254
255 synco
256
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]257 mov.l MIM_L_A, r0
258 mov.l MIM_L_D1, r1
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]259 synco
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]260 mov.l r1, @r0
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]261 synco
262
263 rts
264 nop
265 .align 4
266
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]267RWTCSR_D_1: .word 0xA507
268RWTCSR_D_2: .word 0xA507
269RWTCNT_D: .word 0x5A00
Nobuhiro Iwamatsue58917e2008-09-18 19:34:36 +0900[diff] [blame]270 .align 2
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]271
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]272BBG_PMMR_A: .long 0xFF800010
273BBG_PMSR1_A: .long 0xFF800014
274BBG_PMSR2_A: .long 0xFF800018
275BBG_PMSR3_A: .long 0xFF80001C
276BBG_PMSR4_A: .long 0xFF800020
277BBG_PMSRG_A: .long 0xFF800024
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]278
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]279BBG_PMMR_D_PMSR1: .long 0xffffbffd
280BBG_PMSR1_D: .long 0x00004002
281BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
282BBG_PMSR2_D: .long 0x03de5800
283BBG_PMMR_D_PMSR3: .long 0xfffffff8
284BBG_PMSR3_D: .long 0x00000007
285BBG_PMMR_D_PMSR4: .long 0xdffdfff9
286BBG_PMSR4_D: .long 0x20020006
287BBG_PMMR_D_PMSRG: .long 0xffffffff
288BBG_PMSRG_D: .long 0x00000000
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]289
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]290FRQCR_A: .long FRQCR
291DLLCSR_A: .long 0xffc40010
292FRQCR_D: .long 0x40233035
293DLLCSR_D: .long 0x00000000
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]294
295/* for DDR-SDRAM */
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]296MIM_U_A: .long MIM_1
297MIM_L_A: .long MIM_2
298SCR_U_A: .long SCR_1
299SCR_L_A: .long SCR_2
300STR_U_A: .long STR_1
301STR_L_A: .long STR_2
302SDR_U_A: .long SDR_1
303SDR_L_A: .long SDR_2
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]304
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]305EMRS_A: .long 0xFEC02000
306MRS1_A: .long 0xFEC00B08
307MRS2_A: .long 0xFEC00308
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]308
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]309MIM_U_D: .long 0x00004000
310MIM_L_D0: .long 0x03e80009
311MIM_L_D1: .long 0x03e80209
312SCR_L_D0: .long 0x3
313SCR_L_D1: .long 0x2
314SCR_L_D2: .long 0x2
315SCR_L_D3: .long 0x4
316SCR_L_D4: .long 0x4
317SCR_L_D5: .long 0x0
318STR_L_D: .long 0x000f0000
319SDR_L_D: .long 0x00000400
320EMRS_D: .long 0x0
321MRS1_D: .long 0x0
322MRS2_D: .long 0x0
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]323
324/* Cache Controller */
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]325CCR_A: .long CCR
326MMUCR_A: .long MMUCR
327RWTCNT_A: .long WTCNT
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]328
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]329CCR_D: .long 0x0000090b
330CCR_D_2: .long 0x00000103
331MMUCR_D: .long 0x00000004
332MSTPCR0_D: .long 0x00001001
333MSTPCR2_D: .long 0xffffffff
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]334
335/* local Bus State Controller */
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]336MMSELR_A: .long MMSELR
337BCR_A: .long BCR
338CS0BCR_A: .long CS0BCR
339CS1BCR_A: .long CS1BCR
340CS2BCR_A: .long CS2BCR
341CS4BCR_A: .long CS4BCR
342CS5BCR_A: .long CS5BCR
343CS6BCR_A: .long CS6BCR
344CS0WCR_A: .long CS0WCR
345CS1WCR_A: .long CS1WCR
346CS2WCR_A: .long CS2WCR
347CS4WCR_A: .long CS4WCR
348CS5WCR_A: .long CS5WCR
349CS6WCR_A: .long CS6WCR
350CS5PCR_A: .long CS5PCR
351CS6PCR_A: .long CS6PCR
Yusuke Godacf236022008-03-11 12:55:12 +0900[diff] [blame]352
353MMSELR_D: .long 0xA5A50003
354BCR_D: .long 0x00000000
355CS0BCR_D: .long 0x77777770
356CS1BCR_D: .long 0x77777670
357CS2BCR_D: .long 0x77777770
358CS4BCR_D: .long 0x77777770
359CS5BCR_D: .long 0x77777670
360CS6BCR_D: .long 0x77777770
361CS0WCR_D: .long 0x00020006
362CS1WCR_D: .long 0x00232304
363CS2WCR_D: .long 0x7777770F
364CS4WCR_D: .long 0x7777770F
365CS5WCR_D: .long 0x00101006
366CS6WCR_D: .long 0x77777703
367CS5PCR_D: .long 0x77000000
368CS6PCR_D: .long 0x77000000
369
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]370REPEAT0_R3: .long 0x00002000
371REPEAT0_R1: .long 0x0000200