blob: 9c8e9f0e220c138ec924213e939c2c2ddaaf8146 [file] [log] [blame]
Andrew Davis5c12edd2023-04-11 13:24:57 -05001// SPDX-License-Identifier: GPL-2.0-only
Lokesh Vutlafe2d1d82018-03-16 18:52:20 +05302/*
3 * Copyright (c) 2016 BayLibre, Inc.
Lokesh Vutlafe2d1d82018-03-16 18:52:20 +05304 */
5/dts-v1/;
6#include "da850.dtsi"
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9
10/ {
11 model = "DA850/AM1808/OMAP-L138 LCDK";
12 compatible = "ti,da850-lcdk", "ti,da850";
13
14 aliases {
15 serial2 = &serial2;
16 ethernet0 = &eth0;
17 };
18
19 chosen {
Adam Ford549cf9f2019-11-13 09:46:32 -060020 stdout-path = &serial2;
Lokesh Vutlafe2d1d82018-03-16 18:52:20 +053021 };
22
Adam Ford80699302018-12-03 08:29:43 -060023 memory@c0000000 {
24 /* 128 MB DDR2 SDRAM @ 0xc0000000 */
Lokesh Vutlafe2d1d82018-03-16 18:52:20 +053025 reg = <0xc0000000 0x08000000>;
26 };
27
28 reserved-memory {
29 #address-cells = <1>;
30 #size-cells = <1>;
31 ranges;
32
33 dsp_memory_region: dsp-memory@c3000000 {
34 compatible = "shared-dma-pool";
35 reg = <0xc3000000 0x1000000>;
36 reusable;
37 status = "okay";
38 };
39 };
40
41 sound {
42 compatible = "simple-audio-card";
43 simple-audio-card,name = "DA850/OMAP-L138 LCDK";
44 simple-audio-card,widgets =
45 "Line", "Line In",
46 "Line", "Line Out";
47 simple-audio-card,routing =
48 "LINE1L", "Line In",
49 "LINE1R", "Line In",
50 "Line Out", "LLOUT",
51 "Line Out", "RLOUT";
52 simple-audio-card,format = "dsp_b";
53 simple-audio-card,bitclock-master = <&link0_codec>;
54 simple-audio-card,frame-master = <&link0_codec>;
55 simple-audio-card,bitclock-inversion;
56
57 simple-audio-card,cpu {
58 sound-dai = <&mcasp0>;
59 system-clock-frequency = <24576000>;
60 };
61
62 link0_codec: simple-audio-card,codec {
63 sound-dai = <&tlv320aic3106>;
64 system-clock-frequency = <24576000>;
65 };
66 };
67
68 gpio-keys {
69 compatible = "gpio-keys";
70 autorepeat;
71
72 user1 {
73 label = "GPIO Key USER1";
74 linux,code = <BTN_0>;
75 gpios = <&gpio 36 GPIO_ACTIVE_LOW>;
76 };
77
78 user2 {
79 label = "GPIO Key USER2";
80 linux,code = <BTN_1>;
81 gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
82 };
83 };
84
85 vga-bridge {
86 compatible = "ti,ths8135";
87 #address-cells = <1>;
88 #size-cells = <0>;
89
90 ports {
91 #address-cells = <1>;
92 #size-cells = <0>;
93
94 port@0 {
95 reg = <0>;
96
97 vga_bridge_in: endpoint {
98 remote-endpoint = <&lcdc_out_vga>;
99 };
100 };
101
102 port@1 {
103 reg = <1>;
104
105 vga_bridge_out: endpoint {
106 remote-endpoint = <&vga_con_in>;
107 };
108 };
109 };
110 };
111
112 vga {
113 compatible = "vga-connector";
114
115 ddc-i2c-bus = <&i2c0>;
116
117 port {
118 vga_con_in: endpoint {
119 remote-endpoint = <&vga_bridge_out>;
120 };
121 };
122 };
123};
124
Adam Ford80699302018-12-03 08:29:43 -0600125&ref_clk {
126 clock-frequency = <24000000>;
127};
128
Lokesh Vutlafe2d1d82018-03-16 18:52:20 +0530129&pmx_core {
130 status = "okay";
131
132 mcasp0_pins: pinmux_mcasp0_pins {
133 pinctrl-single,bits = <
134 /* AHCLKX AFSX ACLKX */
135 0x00 0x00101010 0x00f0f0f0
136 /* ARX13 ARX14 */
137 0x04 0x00000110 0x00000ff0
138 >;
139 };
140
141 nand_pins: nand_pins {
142 pinctrl-single,bits = <
143 /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */
144 0x1c 0x10110010 0xf0ff00f0
145 /*
146 * EMA_D[0], EMA_D[1], EMA_D[2],
147 * EMA_D[3], EMA_D[4], EMA_D[5],
148 * EMA_D[6], EMA_D[7]
149 */
150 0x24 0x11111111 0xffffffff
151 /*
152 * EMA_D[8], EMA_D[9], EMA_D[10],
153 * EMA_D[11], EMA_D[12], EMA_D[13],
154 * EMA_D[14], EMA_D[15]
155 */
156 0x20 0x11111111 0xffffffff
157 /* EMA_A[1], EMA_A[2] */
158 0x30 0x01100000 0x0ff00000
159 >;
160 };
161};
162
163&serial2 {
164 pinctrl-names = "default";
165 pinctrl-0 = <&serial2_rxtx_pins>;
166 status = "okay";
167};
168
169&wdt {
170 status = "okay";
171};
172
173&rtc0 {
174 status = "okay";
175};
176
177&gpio {
178 status = "okay";
Adam Ford80699302018-12-03 08:29:43 -0600179};
180
181&sata_refclk {
182 status = "okay";
183 clock-frequency = <100000000>;
Lokesh Vutlafe2d1d82018-03-16 18:52:20 +0530184};
185
186&sata {
187 status = "okay";
188};
189
190&mdio {
191 pinctrl-names = "default";
192 pinctrl-0 = <&mdio_pins>;
193 bus_freq = <2200000>;
194 status = "okay";
195};
196
197&eth0 {
198 pinctrl-names = "default";
199 pinctrl-0 = <&mii_pins>;
200 status = "okay";
201};
202
203&mmc0 {
204 max-frequency = <50000000>;
205 bus-width = <4>;
206 pinctrl-names = "default";
207 pinctrl-0 = <&mmc0_pins>;
208 cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>;
209 status = "okay";
210};
211
212&i2c0 {
213 pinctrl-names = "default";
214 pinctrl-0 = <&i2c0_pins>;
215 clock-frequency = <100000>;
216 status = "okay";
217
218 tlv320aic3106: tlv320aic3106@18 {
219 #sound-dai-cells = <0>;
220 compatible = "ti,tlv320aic3106";
221 reg = <0x18>;
222 status = "okay";
223 };
224};
225
226&mcasp0 {
227 #sound-dai-cells = <0>;
228 pinctrl-names = "default";
229 pinctrl-0 = <&mcasp0_pins>;
230 status = "okay";
231
232 op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */
233 tdm-slots = <2>;
234 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
235 0 0 0 0
236 0 0 0 0
237 0 0 0 0
238 0 1 2 0
239 >;
240 tx-num-evt = <32>;
241 rx-num-evt = <32>;
242};
243
244&usb_phy {
245 status = "okay";
246};
247
248&usb0 {
249 status = "okay";
250};
251
252&usb1 {
253 status = "okay";
254};
255
256&aemif {
257 pinctrl-names = "default";
258 pinctrl-0 = <&nand_pins>;
259 status = "okay";
260 cs3 {
261 #address-cells = <2>;
262 #size-cells = <1>;
263 clock-ranges;
264 ranges;
265
266 ti,cs-chipselect = <3>;
267
268 nand@2000000,0 {
269 compatible = "ti,davinci-nand";
270 #address-cells = <1>;
271 #size-cells = <1>;
272 reg = <0 0x02000000 0x02000000
273 1 0x00000000 0x00008000>;
274
275 ti,davinci-chipselect = <1>;
276 ti,davinci-mask-ale = <0>;
277 ti,davinci-mask-cle = <0>;
278 ti,davinci-mask-chipsel = <0>;
279
280 ti,davinci-nand-buswidth = <16>;
281 ti,davinci-ecc-mode = "hw";
282 ti,davinci-ecc-bits = <4>;
283 ti,davinci-nand-use-bbt;
284
285 /*
286 * The OMAP-L132/L138 Bootloader doc SPRAB41E reads:
287 * "To boot from NAND Flash, the AIS should be written
288 * to NAND block 1 (NAND block 0 is not used by default)".
289 * The same doc mentions that for ROM "Silicon Revision 2.1",
290 * "Updated NAND boot mode to offer boot from block 0 or block 1".
291 * However the limitaion is left here by default for compatibility
292 * with older silicon and because it needs new boot pin settings
293 * not possible in stock LCDK.
294 */
295 partitions {
296 compatible = "fixed-partitions";
297 #address-cells = <1>;
298 #size-cells = <1>;
299
300 partition@0 {
301 label = "u-boot env";
302 reg = <0 0x020000>;
303 };
304 partition@20000 {
305 /* The LCDK defaults to booting from this partition */
306 label = "u-boot";
307 reg = <0x020000 0x080000>;
308 };
309 partition@a0000 {
310 label = "free space";
311 reg = <0x0a0000 0>;
312 };
313 };
314 };
315 };
316};
317
318&prictrl {
319 status = "okay";
320};
321
322&memctrl {
323 status = "okay";
324};
325
326&lcdc {
327 status = "okay";
328 pinctrl-names = "default";
329 pinctrl-0 = <&lcd_pins>;
330
331 port {
332 lcdc_out_vga: endpoint {
333 remote-endpoint = <&vga_bridge_in>;
334 };
335 };
336};
337
338&vpif {
339 pinctrl-names = "default";
340 pinctrl-0 = <&vpif_capture_pins>;
341 status = "okay";
342};
343
344&dsp {
345 memory-region = <&dsp_memory_region>;
346 status = "okay";
347};