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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Macpaul Lin01cfa112010-10-19 17:05:51 +08002/*
3 * Copyright (C) 2011 Andes Technology Corporation
4 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
5 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
Macpaul Lin01cfa112010-10-19 17:05:51 +08006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Masahiro Yamada499a5382015-07-15 20:59:28 +090011#include <asm/arch-ag101/ag101.h>
Macpaul Lin01cfa112010-10-19 17:05:51 +080012
13/*
14 * CPU and Board Configuration Options
15 */
Macpaul Lin01cfa112010-10-19 17:05:51 +080016#define CONFIG_USE_INTERRUPT
17
rickf1113c92017-05-18 14:37:53 +080018#define CONFIG_BOOTP_SERVERIP
ken kuo3756a372013-06-08 11:14:12 +080019
Macpaul Lin01cfa112010-10-19 17:05:51 +080020#ifndef CONFIG_SKIP_LOWLEVEL_INIT
21#define CONFIG_MEM_REMAP
22#endif
23
24#ifdef CONFIG_SKIP_LOWLEVEL_INIT
rick2492bfc2017-04-17 14:41:58 +080025#ifdef CONFIG_OF_CONTROL
26#undef CONFIG_OF_SEPARATE
rick2492bfc2017-04-17 14:41:58 +080027#endif
Kun-Hua Huang89299e22015-08-24 14:52:35 +080028#endif
Macpaul Lin01cfa112010-10-19 17:05:51 +080029
30/*
31 * Timer
32 */
Macpaul Lin01cfa112010-10-19 17:05:51 +080033#define CONFIG_SYS_CLK_FREQ 39062500
34#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
35
36/*
37 * Use Externel CLOCK or PCLK
38 */
39#undef CONFIG_FTRTC010_EXTCLK
40
41#ifndef CONFIG_FTRTC010_EXTCLK
42#define CONFIG_FTRTC010_PCLK
43#endif
44
45#ifdef CONFIG_FTRTC010_EXTCLK
46#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
47#else
48#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
49#endif
50
51#define TIMER_LOAD_VAL 0xffffffff
52
53/*
54 * Real Time Clock
55 */
56#define CONFIG_RTC_FTRTC010
57
58/*
59 * Real Time Clock Divider
60 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
61 */
62#define OSC_5MHZ (5*1000000)
63#define OSC_CLK (4*OSC_5MHZ)
64#define RTC_DIV_COUNT (0.5) /* Why?? */
65
66/*
67 * Serial console configuration
68 */
69
70/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
Macpaul Lin01cfa112010-10-19 17:05:51 +080071#define CONFIG_SYS_NS16550_SERIAL
72#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
rick2492bfc2017-04-17 14:41:58 +080073#ifndef CONFIG_DM_SERIAL
Macpaul Lin01cfa112010-10-19 17:05:51 +080074#define CONFIG_SYS_NS16550_REG_SIZE -4
rick2492bfc2017-04-17 14:41:58 +080075#endif
Macpaul Lin01cfa112010-10-19 17:05:51 +080076#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
77
Macpaul Lin01cfa112010-10-19 17:05:51 +080078/*
Macpaul Lin01cfa112010-10-19 17:05:51 +080079 * Miscellaneous configurable options
80 */
Macpaul Lin01cfa112010-10-19 17:05:51 +080081
Macpaul Lin01cfa112010-10-19 17:05:51 +080082/*
Macpaul Lin01cfa112010-10-19 17:05:51 +080083 * AHB Controller configuration
84 */
85#define CONFIG_FTAHBC020S
86
87#ifdef CONFIG_FTAHBC020S
88#include <faraday/ftahbc020s.h>
89
90/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
91#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
92
93/*
94 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
95 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
96 * in C language.
97 */
98#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
99 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
100 FTAHBC020S_SLAVE_BSR_SIZE(0xb))
101#endif
102
103/*
104 * Watchdog
105 */
106#define CONFIG_FTWDT010_WATCHDOG
107
108/*
109 * PMU Power controller configuration
110 */
111#define CONFIG_PMU
112#define CONFIG_FTPMU010_POWER
113
114#ifdef CONFIG_FTPMU010_POWER
115#include <faraday/ftpmu010.h>
116#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
117#define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \
118 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
119 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
120 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
121 FTPMU010_SDRAMHTC_CKE_DCSR | \
122 FTPMU010_SDRAMHTC_DQM_DCSR | \
123 FTPMU010_SDRAMHTC_SDCLK_DCSR)
124#endif
125
126/*
127 * SDRAM controller configuration
128 */
129#define CONFIG_FTSDMC021
130
131#ifdef CONFIG_FTSDMC021
132#include <faraday/ftsdmc021.h>
133
134#define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \
135 FTSDMC021_TP1_TRP(1) | \
136 FTSDMC021_TP1_TRCD(1) | \
137 FTSDMC021_TP1_TRF(3) | \
138 FTSDMC021_TP1_TWR(1) | \
139 FTSDMC021_TP1_TCL(2))
140
141#define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \
142 FTSDMC021_TP2_INI_REFT(8) | \
143 FTSDMC021_TP2_REF_INTV(0x180))
144
145/*
146 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
147 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
148 * C language.
149 */
150#define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \
151 FTSDMC021_CR1_DSZ(3) | \
152 FTSDMC021_CR1_MBW(2) | \
153 FTSDMC021_CR1_BNKSIZE(6))
154
155#define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \
156 FTSDMC021_CR2_IREF | \
157 FTSDMC021_CR2_ISMR)
158
159#define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
160#define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \
161 CONFIG_SYS_FTSDMC021_BANK0_BASE)
162
ken kuo7abab272013-06-08 11:14:09 +0800163#define CONFIG_SYS_FTSDMC021_BANK1_BASE \
164 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
165#define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \
166 CONFIG_SYS_FTSDMC021_BANK1_BASE)
Macpaul Lin01cfa112010-10-19 17:05:51 +0800167#endif
168
169/*
170 * Physical Memory Map
171 */
Kun-Hua Huang89299e22015-08-24 14:52:35 +0800172#ifdef CONFIG_SKIP_LOWLEVEL_INIT
173#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
174#else
175#ifdef CONFIG_MEM_REMAP
176#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
177#else
178#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
Macpaul Lin01cfa112010-10-19 17:05:51 +0800179#endif
Macpaul Lin01cfa112010-10-19 17:05:51 +0800180#endif
Kun-Hua Huang89299e22015-08-24 14:52:35 +0800181
ken kuo7abab272013-06-08 11:14:09 +0800182#define PHYS_SDRAM_1 \
183 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
Macpaul Lin01cfa112010-10-19 17:05:51 +0800184
Kun-Hua Huang89299e22015-08-24 14:52:35 +0800185#ifdef CONFIG_SKIP_LOWLEVEL_INIT
186#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
187#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
188#else
189#ifdef CONFIG_MEM_REMAP
190#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
191#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
192#else
193#define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */
194#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
195#endif
196#endif
Macpaul Lin01cfa112010-10-19 17:05:51 +0800197
198#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
199
200#ifdef CONFIG_MEM_REMAP
201#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
202 GENERATED_GBL_DATA_SIZE)
203#else
204#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
205 GENERATED_GBL_DATA_SIZE)
206#endif /* CONFIG_MEM_REMAP */
207
208/*
Macpaul Lin01cfa112010-10-19 17:05:51 +0800209 * Static memory controller configuration
210 */
211#define CONFIG_FTSMC020
212
213#ifdef CONFIG_FTSMC020
214#include <faraday/ftsmc020.h>
215
216#define CONFIG_SYS_FTSMC020_CONFIGS { \
217 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
218 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
219}
220
221#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
222#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
223 FTSMC020_BANK_SIZE_32M | \
224 FTSMC020_BANK_MBW_32)
225
226#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
227 FTSMC020_TPR_AST(1) | \
228 FTSMC020_TPR_CTW(1) | \
229 FTSMC020_TPR_ATI(1) | \
230 FTSMC020_TPR_AT2(1) | \
231 FTSMC020_TPR_WTC(1) | \
232 FTSMC020_TPR_AHT(1) | \
233 FTSMC020_TPR_TRNA(1))
234#endif
235
236/*
237 * FLASH on ADP_AG101P is connected to BANK0
238 * Just disalbe the other BANK to avoid detection error.
239 */
240#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
241 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
242 FTSMC020_BANK_SIZE_32M | \
243 FTSMC020_BANK_MBW_32)
244
245#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
246 FTSMC020_TPR_CTW(3) | \
247 FTSMC020_TPR_ATI(0xf) | \
248 FTSMC020_TPR_AT2(3) | \
249 FTSMC020_TPR_WTC(3) | \
250 FTSMC020_TPR_AHT(3) | \
251 FTSMC020_TPR_TRNA(0xf))
252
253#define FTSMC020_BANK1_CONFIG (0x00)
254#define FTSMC020_BANK1_TIMING (0x00)
255#endif /* CONFIG_FTSMC020 */
256
257/*
258 * FLASH and environment organization
259 */
260/* use CFI framework */
Macpaul Lin01cfa112010-10-19 17:05:51 +0800261
262#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Kun-Hua Huang89299e22015-08-24 14:52:35 +0800263#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
Macpaul Lin01cfa112010-10-19 17:05:51 +0800264
265/* support JEDEC */
266
267/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
268#ifdef CONFIG_SKIP_LOWLEVEL_INIT
Kun-Hua Huang89299e22015-08-24 14:52:35 +0800269#define PHYS_FLASH_1 0x80000000 /* BANK 0 */
270#else
Macpaul Lin01cfa112010-10-19 17:05:51 +0800271#ifdef CONFIG_MEM_REMAP
272#define PHYS_FLASH_1 0x80000000 /* BANK 0 */
273#else
274#define PHYS_FLASH_1 0x00000000 /* BANK 0 */
Kun-Hua Huang89299e22015-08-24 14:52:35 +0800275#endif
Macpaul Lin01cfa112010-10-19 17:05:51 +0800276#endif /* CONFIG_MEM_REMAP */
Macpaul Lin01cfa112010-10-19 17:05:51 +0800277
278#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
279#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
280#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
281
282#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
283#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
284
285/* max number of memory banks */
286/*
287 * There are 4 banks supported for this Controller,
288 * but we have only 1 bank connected to flash on board
289 */
rickf1113c92017-05-18 14:37:53 +0800290#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
Macpaul Lin01cfa112010-10-19 17:05:51 +0800291#define CONFIG_SYS_MAX_FLASH_BANKS 1
rickf1113c92017-05-18 14:37:53 +0800292#endif
Kun-Hua Huang89299e22015-08-24 14:52:35 +0800293#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
Macpaul Lin01cfa112010-10-19 17:05:51 +0800294
295/* max number of sectors on one chip */
Kun-Hua Huang89299e22015-08-24 14:52:35 +0800296#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
Kun-Hua Huang89299e22015-08-24 14:52:35 +0800297#define CONFIG_SYS_MAX_FLASH_SECT 512
Macpaul Lin01cfa112010-10-19 17:05:51 +0800298
299/* environments */
Macpaul Lin01cfa112010-10-19 17:05:51 +0800300
rickf1113c92017-05-18 14:37:53 +0800301/*
302 * For booting Linux, the board info and command line data
303 * have to be in the first 16 MB of memory, since this is
304 * the maximum mapped by the Linux kernel during initialization.
305 */
306
307/* Initial Memory map for Linux*/
308#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
309/* Increase max gunzip size */
310#define CONFIG_SYS_BOOTM_LEN (64 << 20)
311
Macpaul Lin01cfa112010-10-19 17:05:51 +0800312#endif /* __CONFIG_H */