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wdenkaffae2b2002-08-17 09:36:01 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkaffae2b2002-08-17 09:36:01 +00006 */
7
8#include <common.h>
9#include <mpc8xx.h>
10
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020011flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
wdenkaffae2b2002-08-17 09:36:01 +000012
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +020013#if defined(CONFIG_ENV_IS_IN_FLASH)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020014# ifndef CONFIG_ENV_ADDR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020015# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
wdenkaffae2b2002-08-17 09:36:01 +000016# endif
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020017# ifndef CONFIG_ENV_SIZE
18# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
wdenkaffae2b2002-08-17 09:36:01 +000019# endif
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020020# ifndef CONFIG_ENV_SECT_SIZE
21# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
wdenkaffae2b2002-08-17 09:36:01 +000022# endif
23#endif
24
25/*-----------------------------------------------------------------------
26 * Functions
27 */
28static ulong flash_get_size (vu_long *addr, flash_info_t *info);
29static int write_word (flash_info_t *info, ulong dest, ulong data);
30static void flash_get_offsets (ulong base, flash_info_t *info);
31
32/*-----------------------------------------------------------------------
33 */
34
35unsigned long flash_init (void)
36{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020037 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
wdenkaffae2b2002-08-17 09:36:01 +000038 volatile memctl8xx_t *memctl = &immap->im_memctl;
39 volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE;
40 unsigned long size;
41 int i;
42
43 /* Init: enable write,
44 * or we cannot even write flash commands
45 */
46 bcsr->bd_ctrl |= BD_CTRL_FLWE;
47
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020048 for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
wdenkaffae2b2002-08-17 09:36:01 +000049 flash_info[i].flash_id = FLASH_UNKNOWN;
50 }
51
52 /* Static FLASH Bank configuration here - FIXME XXX */
53
54 size = flash_get_size((vu_long *)FLASH_BASE, &flash_info[0]);
55
56 if (flash_info[0].flash_id == FLASH_UNKNOWN) {
57 printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
58 size, size<<20);
59 }
60
61 /* Remap FLASH according to real size */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020062 memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
63 memctl->memc_br1 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
wdenkaffae2b2002-08-17 09:36:01 +000064 (memctl->memc_br1 & ~(BR_BA_MSK));
65
66 /* Re-do sizing to get full correct info */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020067 size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
wdenkaffae2b2002-08-17 09:36:01 +000068
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020069 flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
wdenkaffae2b2002-08-17 09:36:01 +000070
71 flash_info[0].size = size;
72
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020073#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
wdenkaffae2b2002-08-17 09:36:01 +000074 /* monitor protection ON by default */
75 flash_protect(FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020076 CONFIG_SYS_MONITOR_BASE,
77 CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
wdenkaffae2b2002-08-17 09:36:01 +000078 &flash_info[0]);
79#endif
80
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +020081#ifdef CONFIG_ENV_IS_IN_FLASH
wdenkaffae2b2002-08-17 09:36:01 +000082 /* ENV protection ON by default */
83 flash_protect(FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020084 CONFIG_ENV_ADDR,
85 CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
wdenkaffae2b2002-08-17 09:36:01 +000086 &flash_info[0]);
87#endif
88 return (size);
89}
90
91/*-----------------------------------------------------------------------
92 */
93static void flash_get_offsets (ulong base, flash_info_t *info)
94{
95 int i;
96
97 /* all possible flash types
98 * (28F016SV, 28F160S3, 28F320S3)
99 * have the same erase block size: 64 kB per chip,
100 * of 128 kB per bank
101 */
102
103 /* set up sector start address table */
104 for (i = 0; i < info->sector_count; i++) {
105 info->start[i] = base;
106 base += 0x00020000;
107 }
108}
109
110/*-----------------------------------------------------------------------
111 */
112void flash_print_info (flash_info_t *info)
113{
114 int i;
115
116 if (info->flash_id == FLASH_UNKNOWN) {
117 printf ("missing or unknown FLASH type\n");
118 return;
119 }
120
121 switch (info->flash_id & FLASH_VENDMASK) {
122 case FLASH_MAN_INTEL: printf ("Intel "); break;
123 default: printf ("Unknown Vendor "); break;
124 }
125
126 switch (info->flash_id & FLASH_TYPEMASK) {
127 case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
128 break;
129 case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
130 break;
131 case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
132 break;
133 default: printf ("Unknown Chip Type\n");
134 break;
135 }
136
137 printf (" Size: %ld MB in %d Sectors\n",
138 info->size >> 20, info->sector_count);
139
140 printf (" Sector Start Addresses:");
141 for (i=0; i<info->sector_count; ++i) {
142 if ((i % 5) == 0)
143 printf ("\n ");
144 printf (" %08lX%s",
145 info->start[i],
146 info->protect[i] ? " (RO)" : " "
147 );
148 }
149 printf ("\n");
150 return;
151}
152
153/*-----------------------------------------------------------------------
154 */
155
156
157/*-----------------------------------------------------------------------
158 */
159
160/*
161 * The following code cannot be run from FLASH!
162 */
163
164static ulong flash_get_size (vu_long *addr, flash_info_t *info)
165{
166 short i;
167 ulong value;
168 ulong base = (ulong)addr;
169
170 /* Write "Intelligent Identifier" command: read Manufacturer ID */
171 *addr = 0x90909090;
172
173 value = addr[0];
174 switch (value) {
175 case (MT_MANUFACT & 0x00FF00FF): /* MT or => Intel */
176 case (INTEL_ALT_MANU & 0x00FF00FF):
177 info->flash_id = FLASH_MAN_INTEL;
178 break;
179 default:
180 info->flash_id = FLASH_UNKNOWN;
181 info->sector_count = 0;
182 info->size = 0;
183 return (0); /* no or unknown flash */
184 }
185
186 value = addr[1]; /* device ID */
187
188 switch (value) {
189 case (INTEL_ID_28F016S):
190 info->flash_id += FLASH_28F016SV;
191 info->sector_count = 32;
192 info->size = 0x00400000;
193 break; /* => 2x2 MB */
194
195 case (INTEL_ID_28F160S3):
196 info->flash_id += FLASH_28F160S3;
197 info->sector_count = 32;
198 info->size = 0x00400000;
199 break; /* => 2x2 MB */
200
201 case (INTEL_ID_28F320S3):
202 info->flash_id += FLASH_28F320S3;
203 info->sector_count = 64;
204 info->size = 0x00800000;
205 break; /* => 2x4 MB */
206
207 default:
208 info->flash_id = FLASH_UNKNOWN;
209 return (0); /* => no or unknown flash */
210
211 }
212
213 /* set up sector start address table */
214 for (i = 0; i < info->sector_count; i++) {
215 info->start[i] = base + (i * 0x00020000);
216 /* don't know how to check sector protection */
217 info->protect[i] = 0;
218 }
219
220 /*
221 * Prevent writes to uninitialized FLASH.
222 */
223 if (info->flash_id != FLASH_UNKNOWN) {
224 addr = (vu_long *)info->start[0];
225
226 *addr = 0xFFFFFF; /* reset bank to read array mode */
227 }
228
229 return (info->size);
230}
231
232
233/*-----------------------------------------------------------------------
234 */
235
236int flash_erase (flash_info_t *info, int s_first, int s_last)
237{
238 int flag, prot, sect;
239 ulong start, now, last;
240
241 if ((s_first < 0) || (s_first > s_last)) {
242 if (info->flash_id == FLASH_UNKNOWN) {
243 printf ("- missing\n");
244 } else {
245 printf ("- no sectors to erase\n");
246 }
247 return 1;
248 }
249
250 if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
251 printf ("Can't erase unknown flash type %08lx - aborted\n",
252 info->flash_id);
253 return 1;
254 }
255
256 prot = 0;
257 for (sect=s_first; sect<=s_last; ++sect) {
258 if (info->protect[sect]) {
259 prot++;
260 }
261 }
262
263 if (prot) {
264 printf ("- Warning: %d protected sectors will not be erased!\n",
265 prot);
266 } else {
267 printf ("\n");
268 }
269
270 start = get_timer (0);
271 last = start;
272
273 /* Start erase on unprotected sectors */
274 for (sect = s_first; sect<=s_last; sect++) {
275 if (info->protect[sect] == 0) { /* not protected */
276 vu_long *addr = (vu_long *)(info->start[sect]);
277
278 /* Disable interrupts which might cause a timeout here */
279 flag = disable_interrupts();
280
281 /* Single Block Erase Command */
282 *addr = 0x20202020;
283 /* Confirm */
284 *addr = 0xD0D0D0D0;
285 /* Resume Command, as per errata update */
286 *addr = 0xD0D0D0D0;
287
288 /* re-enable interrupts if necessary */
289 if (flag)
290 enable_interrupts();
291
292 /* wait at least 80us - let's wait 1 ms */
293 udelay (1000);
294
295 while ((*addr & 0x00800080) != 0x00800080) {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200296 if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
wdenkaffae2b2002-08-17 09:36:01 +0000297 printf ("Timeout\n");
298 *addr = 0xFFFFFFFF; /* reset bank */
299 return 1;
300 }
301 /* show that we're waiting */
302 if ((now - last) > 1000) { /* every second */
303 putc ('.');
304 last = now;
305 }
306 }
307
308 /* reset to read mode */
309 *addr = 0xFFFFFFFF;
310 }
311 }
312
313 printf (" done\n");
314 return 0;
315}
316
317/*-----------------------------------------------------------------------
318 * Copy memory to flash, returns:
319 * 0 - OK
320 * 1 - write timeout
321 * 2 - Flash not erased
322 */
323
324int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
325{
326 ulong cp, wp, data;
327 int i, l, rc;
328
329 wp = (addr & ~3); /* get lower word aligned address */
330
331 /*
332 * handle unaligned start bytes
333 */
334 if ((l = addr - wp) != 0) {
335 data = 0;
336 for (i=0, cp=wp; i<l; ++i, ++cp) {
337 data = (data << 8) | (*(uchar *)cp);
338 }
339 for (; i<4 && cnt>0; ++i) {
340 data = (data << 8) | *src++;
341 --cnt;
342 ++cp;
343 }
344 for (; cnt==0 && i<4; ++i, ++cp) {
345 data = (data << 8) | (*(uchar *)cp);
346 }
347
348 if ((rc = write_word(info, wp, data)) != 0) {
349 return (rc);
350 }
351 wp += 4;
352 }
353
354 /*
355 * handle word aligned part
356 */
357 while (cnt >= 4) {
358 data = 0;
359 for (i=0; i<4; ++i) {
360 data = (data << 8) | *src++;
361 }
362 if ((rc = write_word(info, wp, data)) != 0) {
363 return (rc);
364 }
365 wp += 4;
366 cnt -= 4;
367 }
368
369 if (cnt == 0) {
370 return (0);
371 }
372
373 /*
374 * handle unaligned tail bytes
375 */
376 data = 0;
377 for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
378 data = (data << 8) | *src++;
379 --cnt;
380 }
381 for (; i<4; ++i, ++cp) {
382 data = (data << 8) | (*(uchar *)cp);
383 }
384
385 return (write_word(info, wp, data));
386}
387
388/*-----------------------------------------------------------------------
389 * Write a word to Flash, returns:
390 * 0 - OK
391 * 1 - write timeout
392 * 2 - Flash not erased
393 */
394static int write_word (flash_info_t *info, ulong dest, ulong data)
395{
396 vu_long *addr = (vu_long *)dest;
397 ulong start, csr;
398 int flag;
399
400 /* Check if Flash is (sufficiently) erased */
401 if ((*addr & data) != data) {
402 return (2);
403 }
404 /* Disable interrupts which might cause a timeout here */
405 flag = disable_interrupts();
406
407 /* Write Command */
408 *addr = 0x10101010;
409
410 /* Write Data */
411 *addr = data;
412
413 /* re-enable interrupts if necessary */
414 if (flag)
415 enable_interrupts();
416
417 /* data polling for D7 */
418 start = get_timer (0);
419 flag = 0;
420 while (((csr = *addr) & 0x00800080) != 0x00800080) {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200421 if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
wdenkaffae2b2002-08-17 09:36:01 +0000422 flag = 1;
423 break;
424 }
425 }
426 if (csr & 0x00400040) {
427printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
428 flag = 1;
429 }
430
431 /* Clear Status Registers Command */
432 *addr = 0x50505050;
433 /* Reset to read array mode */
434 *addr = 0xFFFFFFFF;
435
436 return (flag);
437}
438
439/*-----------------------------------------------------------------------
440 */