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git01.mediatek.com / filogic / uboot / 8bac8e982bf1ff44f7c362b37107f0e826613b38 / . / arch / arm / dts / k3-j721e-common-proc-board-u-boot.dtsi
blob: 867ec2bb1affbd1eeb5d62e0e4aee437a3c86dd5 [file] [log] [blame]
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
4 */
5
Vignesh Raghavendra268dad22019-12-04 22:17:24 +0530[diff] [blame]6#include <dt-bindings/net/ti-dp83867.h>
7
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]8/ {
9 chosen {
10 stdout-path = "serial2:115200n8";
11 tick-timer = &timer1;
12 };
Vignesh Raghavendra268dad22019-12-04 22:17:24 +0530[diff] [blame]13
14 aliases {
15 ethernet0 = &cpsw_port1;
Lokesh Vutla62eada12021-02-01 11:26:40 +0530[diff] [blame]16 spi0 = &ospi0;
17 spi1 = &ospi1;
18 remoteproc0 = &mcu_r5fss0_core0;
19 remoteproc1 = &mcu_r5fss0_core1;
20 remoteproc2 = &main_r5fss0_core0;
21 remoteproc3 = &main_r5fss0_core1;
22 remoteproc4 = &main_r5fss1_core0;
23 remoteproc5 = &main_r5fss1_core1;
24 remoteproc6 = &c66_0;
25 remoteproc7 = &c66_1;
26 remoteproc8 = &c71_0;
27 i2c0 = &wkup_i2c0;
28 i2c1 = &mcu_i2c0;
29 i2c2 = &mcu_i2c1;
30 i2c3 = &main_i2c0;
Vignesh Raghavendra268dad22019-12-04 22:17:24 +0530[diff] [blame]31 };
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]32};
33
34&cbass_main{
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-pre-ram;
Lokesh Vutla62eada12021-02-01 11:26:40 +0530[diff] [blame]36
Tom Rinif8276452021-09-10 17:37:43 -0400[diff] [blame]37 main_navss: bus@30000000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]38 bootph-pre-ram;
Lokesh Vutla62eada12021-02-01 11:26:40 +0530[diff] [blame]39 };
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]40};
41
42&cbass_mcu_wakeup {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]43 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]44
45 timer1: timer@40400000 {
46 compatible = "ti,omap5430-timer";
47 reg = <0x0 0x40400000 0x0 0x80>;
48 ti,timer-alwon;
Tero Kristo94388c82021-06-11 11:45:27 +0300[diff] [blame]49 clock-frequency = <250000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]50 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]51 };
Vignesh Raghavendra268dad22019-12-04 22:17:24 +0530[diff] [blame]52
Tom Rinif8276452021-09-10 17:37:43 -0400[diff] [blame]53 mcu_navss: bus@28380000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]54 bootph-pre-ram;
Vignesh Raghavendra268dad22019-12-04 22:17:24 +0530[diff] [blame]55
Vignesh Raghavendra01250d82020-07-07 13:43:35 +0530[diff] [blame]56 ringacc@2b800000 {
Vignesh Raghavendra7bd02882021-06-07 19:47:51 +0530[diff] [blame]57 reg = <0x0 0x2b800000 0x0 0x400000>,
58 <0x0 0x2b000000 0x0 0x400000>,
59 <0x0 0x28590000 0x0 0x100>,
60 <0x0 0x2a500000 0x0 0x40000>,
61 <0x0 0x28440000 0x0 0x40000>;
62 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]63 bootph-pre-ram;
Vignesh Raghavendra268dad22019-12-04 22:17:24 +0530[diff] [blame]64 };
65
Vignesh Raghavendra01250d82020-07-07 13:43:35 +0530[diff] [blame]66 dma-controller@285c0000 {
Vignesh Raghavendra7bd02882021-06-07 19:47:51 +0530[diff] [blame]67 reg = <0x0 0x285c0000 0x0 0x100>,
68 <0x0 0x284c0000 0x0 0x4000>,
69 <0x0 0x2a800000 0x0 0x40000>,
70 <0x0 0x284a0000 0x0 0x4000>,
71 <0x0 0x2aa00000 0x0 0x40000>,
72 <0x0 0x28400000 0x0 0x2000>;
73 reg-names = "gcfg", "rchan", "rchanrt", "tchan",
74 "tchanrt", "rflow";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-pre-ram;
Vignesh Raghavendra268dad22019-12-04 22:17:24 +0530[diff] [blame]76 };
77 };
Lokesh Vutla62eada12021-02-01 11:26:40 +0530[diff] [blame]78
79 chipid@43000014 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]80 bootph-pre-ram;
Lokesh Vutla62eada12021-02-01 11:26:40 +0530[diff] [blame]81 };
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]82};
83
84&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]86};
87
88&dmsc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]89 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]90 k3_sysreset: sysreset-controller {
91 compatible = "ti,sci-sysreset";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]92 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]93 };
94};
95
96&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]97 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]98};
99
100&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]101 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]102};
103
104&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]105 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]106};
107
108&wkup_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]109 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]110};
111
112&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]113 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]114};
115
116&main_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]117 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]118};
119
120&mcu_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]121 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]122};
123
124&main_sdhci0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]125 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]126};
127
128&main_sdhci1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]129 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]130};
Vignesh Raghavendra268dad22019-12-04 22:17:24 +0530[diff] [blame]131
Kishon Vijay Abraham I7f3a3092021-07-21 21:28:40 +0530[diff] [blame]132&wiz3_pll1_refclk {
133 assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>;
134 assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>;
135};
136
Vignesh Raghavendra04ed4932019-11-18 19:16:35 +0530[diff] [blame]137&main_usbss0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]138 bootph-pre-ram;
Vignesh Raghavendra04ed4932019-11-18 19:16:35 +0530[diff] [blame]139};
140
141&usbss0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]142 bootph-pre-ram;
Vignesh Raghavendra04ed4932019-11-18 19:16:35 +0530[diff] [blame]143};
144
145&usb0 {
146 dr_mode = "peripheral";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]147 bootph-pre-ram;
Vignesh Raghavendra04ed4932019-11-18 19:16:35 +0530[diff] [blame]148};
149
Vignesh Raghavendra268dad22019-12-04 22:17:24 +0530[diff] [blame]150&mcu_cpsw {
151 reg = <0x0 0x46000000 0x0 0x200000>,
152 <0x0 0x40f00200 0x0 0x2>;
153 reg-names = "cpsw_nuss", "mac_efuse";
Vignesh Raghavendra3f09ed42020-07-06 13:36:55 +0530[diff] [blame]154 /delete-property/ ranges;
Vignesh Raghavendra268dad22019-12-04 22:17:24 +0530[diff] [blame]155
156 cpsw-phy-sel@40f04040 {
157 compatible = "ti,am654-cpsw-phy-sel";
158 reg= <0x0 0x40f04040 0x0 0x4>;
159 reg-names = "gmii-sel";
160 };
161};
Faiz Abbasc67d3892020-01-16 19:42:21 +0530[diff] [blame]162
163&main_mmc1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]164 bootph-pre-ram;
Faiz Abbasc67d3892020-01-16 19:42:21 +0530[diff] [blame]165};
Andreas Dannenberg0fe40e92020-01-07 13:15:56 +0530[diff] [blame]166
167&wkup_i2c0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]168 bootph-pre-ram;
Andreas Dannenberg0fe40e92020-01-07 13:15:56 +0530[diff] [blame]169};
170
171&wkup_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]172 bootph-pre-ram;
Andreas Dannenberg0fe40e92020-01-07 13:15:56 +0530[diff] [blame]173};
Vignesh Raghavendra8a290cc2020-01-27 23:22:15 +0530[diff] [blame]174
175&main_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]176 bootph-pre-ram;
Vignesh Raghavendra8a290cc2020-01-27 23:22:15 +0530[diff] [blame]177};
178
179&main_i2c0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]180 bootph-pre-ram;
Vignesh Raghavendra8a290cc2020-01-27 23:22:15 +0530[diff] [blame]181};
182
183&exp2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]184 bootph-pre-ram;
Vignesh Raghavendra8a290cc2020-01-27 23:22:15 +0530[diff] [blame]185};
Vignesh Raghavendrada674372020-02-04 11:09:52 +0530[diff] [blame]186
187&mcu_fss0_ospi0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]188 bootph-pre-ram;
Vignesh Raghavendrada674372020-02-04 11:09:52 +0530[diff] [blame]189};
190
191&fss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]192 bootph-pre-ram;
Vignesh Raghavendrada674372020-02-04 11:09:52 +0530[diff] [blame]193};
194
Vaishnav Achath490287c2022-05-09 11:50:12 +0530[diff] [blame]195&hbmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]196 bootph-pre-ram;
Vaishnav Achath490287c2022-05-09 11:50:12 +0530[diff] [blame]197
198 flash@0,0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]199 bootph-pre-ram;
Vaishnav Achath490287c2022-05-09 11:50:12 +0530[diff] [blame]200 };
201};
202
203&hbmc_mux {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]204 bootph-pre-ram;
Vaishnav Achath490287c2022-05-09 11:50:12 +0530[diff] [blame]205};
206
207&wkup_gpio0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]208 bootph-pre-ram;
Vaishnav Achath490287c2022-05-09 11:50:12 +0530[diff] [blame]209};
210
Vignesh Raghavendrada674372020-02-04 11:09:52 +0530[diff] [blame]211&ospi0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]212 bootph-pre-ram;
Vignesh Raghavendrada674372020-02-04 11:09:52 +0530[diff] [blame]213
214 flash@0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]215 bootph-pre-ram;
Vignesh Raghavendrada674372020-02-04 11:09:52 +0530[diff] [blame]216 };
217};
Keerthy71156c92020-03-04 10:09:59 +0530[diff] [blame]218
219&ospi1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]220 bootph-pre-ram;
Keerthy71156c92020-03-04 10:09:59 +0530[diff] [blame]221
222 flash@0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]223 bootph-pre-ram;
Keerthy71156c92020-03-04 10:09:59 +0530[diff] [blame]224 };
225};
226
Vaishnav Achath490287c2022-05-09 11:50:12 +0530[diff] [blame]227&mcu_fss0_hpb0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]228 bootph-pre-ram;
Vaishnav Achath490287c2022-05-09 11:50:12 +0530[diff] [blame]229};
230
231&wkup_gpio_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]232 bootph-pre-ram;
Vaishnav Achath490287c2022-05-09 11:50:12 +0530[diff] [blame]233};
234
Keerthy71156c92020-03-04 10:09:59 +0530[diff] [blame]235&mcu_fss0_ospi1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]236 bootph-pre-ram;
Keerthy71156c92020-03-04 10:09:59 +0530[diff] [blame]237};
Suman Anna90eecec2021-05-18 16:38:25 -0500[diff] [blame]238
239&main_r5fss0 {
240 ti,cluster-mode = <0>;
241};
242
243&main_r5fss1 {
244 ti,cluster-mode = <0>;
245};
Kishon Vijay Abraham I7f3a3092021-07-21 21:28:40 +0530[diff] [blame]246
247&wiz3_pll1_refclk {
248 assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>;
249 assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>;
250};
251
252&serdes_ln_ctrl {
253 u-boot,mux-autoprobe;
254};
255
256&usb_serdes_mux {
257 u-boot,mux-autoprobe;
258};
Aswath Govindrajudcfb97e2022-01-28 13:41:39 +0530[diff] [blame]259
260&serdes0 {
261 /delete-property/ assigned-clocks;
262 /delete-property/ assigned-clock-parents;
263};
264
265&serdes0_pcie_link {
266 assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
267 assigned-clock-parents = <&wiz0_pll1_refclk>;
268};
Aswath Govindraju83a83672022-01-28 13:41:51 +0530[diff] [blame]269
270&serdes0_qsgmii_link {
271 assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
272 assigned-clock-parents = <&wiz0_pll1_refclk>;
273};