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David Wu5f596ae2019-01-02 21:00:55 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4 */
5
David Wu5f596ae2019-01-02 21:00:55 +08006#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -06007#include <log.h>
David Wu5f596ae2019-01-02 21:00:55 +08008#include <dm/pinctrl.h>
9#include <regmap.h>
10#include <syscon.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060011#include <linux/bitops.h>
David Wu5f596ae2019-01-02 21:00:55 +080012
13#include "pinctrl-rockchip.h"
14
15static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
16 {
Jonas Karlman91a62db2025-01-06 21:39:42 +000017 /* gpio2_b7_sel */
David Wu5f596ae2019-01-02 21:00:55 +080018 .num = 2,
19 .pin = 15,
20 .reg = 0x28,
21 .bit = 0,
22 .mask = 0x7
23 }, {
Jonas Karlman91a62db2025-01-06 21:39:42 +000024 /* gpio2_c7_sel */
David Wu5f596ae2019-01-02 21:00:55 +080025 .num = 2,
26 .pin = 23,
27 .reg = 0x30,
28 .bit = 14,
29 .mask = 0x3
Jonas Karlman91a62db2025-01-06 21:39:42 +000030 }, {
31 /* gpio3_b1_sel */
32 .num = 3,
33 .pin = 9,
34 .reg = 0x44,
35 .bit = 2,
36 .mask = 0x3
37 }, {
38 /* gpio3_b2_sel */
39 .num = 3,
40 .pin = 10,
41 .reg = 0x44,
42 .bit = 4,
43 .mask = 0x3
44 }, {
45 /* gpio3_b3_sel */
46 .num = 3,
47 .pin = 11,
48 .reg = 0x44,
49 .bit = 6,
50 .mask = 0x3
51 }, {
52 /* gpio3_b4_sel */
53 .num = 3,
54 .pin = 12,
55 .reg = 0x44,
56 .bit = 8,
57 .mask = 0x3
58 }, {
59 /* gpio3_b5_sel */
60 .num = 3,
61 .pin = 13,
62 .reg = 0x44,
63 .bit = 10,
64 .mask = 0x3
65 }, {
66 /* gpio3_b6_sel */
67 .num = 3,
68 .pin = 14,
69 .reg = 0x44,
70 .bit = 12,
71 .mask = 0x3
72 }, {
73 /* gpio3_b7_sel */
74 .num = 3,
75 .pin = 15,
76 .reg = 0x44,
77 .bit = 14,
78 .mask = 0x3
David Wu5f596ae2019-01-02 21:00:55 +080079 },
80};
81
82static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
83 {
84 /* uart2dbg_rxm0 */
85 .bank_num = 1,
86 .pin = 1,
87 .func = 2,
88 .route_offset = 0x50,
89 .route_val = BIT(16) | BIT(16 + 1),
90 }, {
91 /* uart2dbg_rxm1 */
92 .bank_num = 2,
93 .pin = 1,
94 .func = 1,
95 .route_offset = 0x50,
96 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
97 }, {
98 /* gmac-m1_rxd0 */
99 .bank_num = 1,
100 .pin = 11,
101 .func = 2,
102 .route_offset = 0x50,
103 .route_val = BIT(16 + 2) | BIT(2),
104 }, {
105 /* gmac-m1-optimized_rxd3 */
106 .bank_num = 1,
107 .pin = 14,
108 .func = 2,
109 .route_offset = 0x50,
110 .route_val = BIT(16 + 10) | BIT(10),
111 }, {
112 /* pdm_sdi0m0 */
113 .bank_num = 2,
114 .pin = 19,
115 .func = 2,
116 .route_offset = 0x50,
117 .route_val = BIT(16 + 3),
118 }, {
119 /* pdm_sdi0m1 */
120 .bank_num = 1,
121 .pin = 23,
122 .func = 3,
123 .route_offset = 0x50,
124 .route_val = BIT(16 + 3) | BIT(3),
125 }, {
126 /* spi_rxdm2 */
127 .bank_num = 3,
128 .pin = 2,
129 .func = 4,
130 .route_offset = 0x50,
131 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
132 }, {
133 /* i2s2_sdim0 */
134 .bank_num = 1,
135 .pin = 24,
136 .func = 1,
137 .route_offset = 0x50,
138 .route_val = BIT(16 + 6),
139 }, {
140 /* i2s2_sdim1 */
141 .bank_num = 3,
142 .pin = 2,
143 .func = 6,
144 .route_offset = 0x50,
145 .route_val = BIT(16 + 6) | BIT(6),
146 }, {
147 /* card_iom1 */
148 .bank_num = 2,
149 .pin = 22,
150 .func = 3,
151 .route_offset = 0x50,
152 .route_val = BIT(16 + 7) | BIT(7),
153 }, {
154 /* tsp_d5m1 */
155 .bank_num = 2,
156 .pin = 16,
157 .func = 3,
158 .route_offset = 0x50,
159 .route_val = BIT(16 + 8) | BIT(8),
160 }, {
161 /* cif_data5m1 */
162 .bank_num = 2,
163 .pin = 16,
164 .func = 4,
165 .route_offset = 0x50,
166 .route_val = BIT(16 + 9) | BIT(9),
167 },
168};
169
David Wu3dd7d6c2019-04-16 21:50:55 +0800170static int rk3328_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
171{
172 struct rockchip_pinctrl_priv *priv = bank->priv;
173 int iomux_num = (pin / 8);
174 struct regmap *regmap;
175 int reg, ret, mask, mux_type;
176 u8 bit;
Jagan Teki9e0e6812022-12-14 23:20:56 +0530177 u32 data;
David Wu3dd7d6c2019-04-16 21:50:55 +0800178
179 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
180 ? priv->regmap_pmu : priv->regmap_base;
181
182 /* get basic quadrupel of mux registers and the correct reg inside */
183 mux_type = bank->iomux[iomux_num].type;
184 reg = bank->iomux[iomux_num].offset;
185 reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
186
187 if (bank->recalced_mask & BIT(pin))
188 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
189
David Wu3dd7d6c2019-04-16 21:50:55 +0800190 data = (mask << (bit + 16));
191 data |= (mux & mask) << bit;
192 ret = regmap_write(regmap, reg, data);
193
194 return ret;
195}
196
David Wu5f596ae2019-01-02 21:00:55 +0800197#define RK3328_PULL_OFFSET 0x100
198
199static void rk3328_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
200 int pin_num, struct regmap **regmap,
201 int *reg, u8 *bit)
202{
203 struct rockchip_pinctrl_priv *priv = bank->priv;
204
205 *regmap = priv->regmap_base;
206 *reg = RK3328_PULL_OFFSET;
207 *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
208 *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
209
210 *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
211 *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
212}
213
David Wu2972c452019-04-16 21:57:05 +0800214static int rk3328_set_pull(struct rockchip_pin_bank *bank,
215 int pin_num, int pull)
216{
217 struct regmap *regmap;
218 int reg, ret;
219 u8 bit, type;
220 u32 data;
221
222 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
223 return -ENOTSUPP;
224
225 rk3328_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
226 type = bank->pull_type[pin_num / 8];
227 ret = rockchip_translate_pull_value(type, pull);
228 if (ret < 0) {
229 debug("unsupported pull setting %d\n", pull);
230 return ret;
231 }
232
233 /* enable the write to the equivalent lower bits */
234 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
235 data |= (ret << bit);
236 ret = regmap_write(regmap, reg, data);
237
238 return ret;
239}
240
David Wu5f596ae2019-01-02 21:00:55 +0800241#define RK3328_DRV_GRF_OFFSET 0x200
242
243static void rk3328_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
244 int pin_num, struct regmap **regmap,
245 int *reg, u8 *bit)
246{
247 struct rockchip_pinctrl_priv *priv = bank->priv;
248
249 *regmap = priv->regmap_base;
250 *reg = RK3328_DRV_GRF_OFFSET;
251 *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
252 *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
253
254 *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
255 *bit *= ROCKCHIP_DRV_BITS_PER_PIN;
256}
257
David Wu40a55482019-04-16 21:55:26 +0800258static int rk3328_set_drive(struct rockchip_pin_bank *bank,
259 int pin_num, int strength)
260{
261 struct regmap *regmap;
262 int reg, ret;
263 u32 data;
264 u8 bit;
265 int type = bank->drv[pin_num / 8].drv_type;
266
267 rk3328_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
268 ret = rockchip_translate_drive_value(type, strength);
269 if (ret < 0) {
270 debug("unsupported driver strength %d\n", strength);
271 return ret;
272 }
273
274 /* enable the write to the equivalent lower bits */
275 data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
276 data |= (ret << bit);
277 ret = regmap_write(regmap, reg, data);
278
279 return ret;
280}
281
David Wu5f596ae2019-01-02 21:00:55 +0800282#define RK3328_SCHMITT_BITS_PER_PIN 1
283#define RK3328_SCHMITT_PINS_PER_REG 16
284#define RK3328_SCHMITT_BANK_STRIDE 8
285#define RK3328_SCHMITT_GRF_OFFSET 0x380
286
287static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
288 int pin_num,
289 struct regmap **regmap,
290 int *reg, u8 *bit)
291{
292 struct rockchip_pinctrl_priv *priv = bank->priv;
293
294 *regmap = priv->regmap_base;
295 *reg = RK3328_SCHMITT_GRF_OFFSET;
296
297 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
298 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
299 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
300
301 return 0;
302}
303
David Wu7ae4ec92019-04-16 21:58:13 +0800304static int rk3328_set_schmitt(struct rockchip_pin_bank *bank,
305 int pin_num, int enable)
306{
307 struct regmap *regmap;
308 int reg;
309 u8 bit;
310 u32 data;
311
312 rk3328_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
313 /* enable the write to the equivalent lower bits */
314 data = BIT(bit + 16) | (enable << bit);
315
316 return regmap_write(regmap, reg, data);
317}
318
David Wu5f596ae2019-01-02 21:00:55 +0800319static struct rockchip_pin_bank rk3328_pin_banks[] = {
320 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
321 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
322 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
Jonas Karlman91a62db2025-01-06 21:39:42 +0000323 IOMUX_8WIDTH_2BIT,
David Wu5f596ae2019-01-02 21:00:55 +0800324 IOMUX_WIDTH_3BIT,
325 0),
326 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
327 IOMUX_WIDTH_3BIT,
328 IOMUX_WIDTH_3BIT,
329 0,
330 0),
331};
332
333static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
David Wu71aede02019-04-16 21:50:54 +0800334 .pin_banks = rk3328_pin_banks,
335 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
David Wu71aede02019-04-16 21:50:54 +0800336 .grf_mux_offset = 0x0,
337 .iomux_recalced = rk3328_mux_recalced_data,
338 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
339 .iomux_routes = rk3328_mux_route_data,
340 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
David Wu3dd7d6c2019-04-16 21:50:55 +0800341 .set_mux = rk3328_set_mux,
David Wu2972c452019-04-16 21:57:05 +0800342 .set_pull = rk3328_set_pull,
David Wu40a55482019-04-16 21:55:26 +0800343 .set_drive = rk3328_set_drive,
David Wu7ae4ec92019-04-16 21:58:13 +0800344 .set_schmitt = rk3328_set_schmitt,
David Wu5f596ae2019-01-02 21:00:55 +0800345};
346
347static const struct udevice_id rk3328_pinctrl_ids[] = {
348 {
349 .compatible = "rockchip,rk3328-pinctrl",
350 .data = (ulong)&rk3328_pin_ctrl
351 },
352 { }
353};
354
Walter Lozano2901ac62020-06-25 01:10:04 -0300355U_BOOT_DRIVER(rockchip_rk3328_pinctrl) = {
David Wu5f596ae2019-01-02 21:00:55 +0800356 .name = "rockchip_rk3328_pinctrl",
357 .id = UCLASS_PINCTRL,
358 .of_match = rk3328_pinctrl_ids,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700359 .priv_auto = sizeof(struct rockchip_pinctrl_priv),
David Wu5f596ae2019-01-02 21:00:55 +0800360 .ops = &rockchip_pinctrl_ops,
Simon Glass92882652021-08-07 07:24:04 -0600361#if CONFIG_IS_ENABLED(OF_REAL)
David Wu5f596ae2019-01-02 21:00:55 +0800362 .bind = dm_scan_fdt_dev,
363#endif
364 .probe = rockchip_pinctrl_probe,
365};