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Haavard Skinnemoenb62a4312007-04-14 17:11:49 +02001/*
2 * Copyright (C) 2006 Atmel Corporation
3 *
4 * Configuration settings for the AVR32 Network Gateway
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +02007 */
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Andreas Bießmann94156fa2010-11-04 23:15:30 +000011#include <asm/arch/hardware.h>
Haavard Skinnemoen23f62f12008-05-19 11:36:28 +020012
Andreas Bießmann8a16a192011-04-18 04:12:35 +000013#define CONFIG_AVR32
14#define CONFIG_AT32AP
15#define CONFIG_AT32AP7000
16#define CONFIG_ATNGW100
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +020017
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +020018/*
19 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
20 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
21 * and the PBA bus to run at 1/4 the PLL frequency.
22 */
Andreas Bießmann8a16a192011-04-18 04:12:35 +000023#define CONFIG_PLL
24#define CONFIG_SYS_POWER_MANAGER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020025#define CONFIG_SYS_OSC0_HZ 20000000
26#define CONFIG_SYS_PLL0_DIV 1
27#define CONFIG_SYS_PLL0_MUL 7
28#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
29#define CONFIG_SYS_CLKDIV_CPU 0
30#define CONFIG_SYS_CLKDIV_HSB 1
31#define CONFIG_SYS_CLKDIV_PBA 2
32#define CONFIG_SYS_CLKDIV_PBB 1
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +020033
Haavard Skinnemoenc6f292f2010-08-12 13:52:54 +070034/* Reserve VM regions for SDRAM and NOR flash */
35#define CONFIG_SYS_NR_VM_REGIONS 2
36
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +020037/*
38 * The PLLOPT register controls the PLL like this:
39 * icp = PLLOPT<2>
40 * ivco = PLLOPT<1:0>
41 *
42 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
43 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020044#define CONFIG_SYS_PLL0_OPT 0x04
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +020045
Andreas Bießmann5807e792010-11-04 23:15:31 +000046#define CONFIG_USART_BASE ATMEL_BASE_USART1
47#define CONFIG_USART_ID 1
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +020048/* User serviceable stuff */
Andreas Bießmann8a16a192011-04-18 04:12:35 +000049#define CONFIG_DOS_PARTITION
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +020050
Andreas Bießmann8a16a192011-04-18 04:12:35 +000051#define CONFIG_CMDLINE_TAG
52#define CONFIG_SETUP_MEMORY_TAGS
53#define CONFIG_INITRD_TAG
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +020054
55#define CONFIG_STACKSIZE (2048)
56
57#define CONFIG_BAUDRATE 115200
58#define CONFIG_BOOTARGS \
59 "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2"
60#define CONFIG_BOOTCOMMAND \
61 "fsload; bootm"
62
63/*
64 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
65 * data on the serial line may interrupt the boot sequence.
66 */
67#define CONFIG_BOOTDELAY 1
Andreas Bießmann8a16a192011-04-18 04:12:35 +000068#define CONFIG_AUTOBOOT
69#define CONFIG_AUTOBOOT_KEYED
Wolfgang Denkdd5463b2008-07-16 16:38:59 +020070#define CONFIG_AUTOBOOT_PROMPT \
71 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +020072#define CONFIG_AUTOBOOT_DELAY_STR "d"
73#define CONFIG_AUTOBOOT_STOP_STR " "
74
75/*
76 * After booting the board for the first time, new ethernet addresses
77 * should be generated and assigned to the environment variables
78 * "ethaddr" and "eth1addr". This is normally done during production.
79 */
Andreas Bießmann8a16a192011-04-18 04:12:35 +000080#define CONFIG_OVERWRITE_ETHADDR_ONCE
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +020081
82/*
83 * BOOTP/DHCP options
84 */
85#define CONFIG_BOOTP_SUBNETMASK
86#define CONFIG_BOOTP_GATEWAY
87
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +020088/*
89 * Command line configuration.
90 */
91#include <config_cmd_default.h>
92
93#define CONFIG_CMD_ASKENV
94#define CONFIG_CMD_DHCP
95#define CONFIG_CMD_EXT2
96#define CONFIG_CMD_FAT
97#define CONFIG_CMD_JFFS2
98#define CONFIG_CMD_MMC
Haavard Skinnemoen14682842008-06-20 10:41:05 +020099#define CONFIG_CMD_SF
100#define CONFIG_CMD_SPI
David Brownell6ce352c2008-02-22 12:54:39 -0800101
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +0200102#undef CONFIG_CMD_FPGA
103#undef CONFIG_CMD_SETGETDCR
Wolfgang Denk85c25df2009-04-01 23:34:12 +0200104#undef CONFIG_CMD_SOURCE
David Brownell6ce352c2008-02-22 12:54:39 -0800105#undef CONFIG_CMD_XIMG
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +0200106
Andreas Bießmann8a16a192011-04-18 04:12:35 +0000107#define CONFIG_ATMEL_USART
108#define CONFIG_MACB
109#define CONFIG_PORTMUX_PIO
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200110#define CONFIG_SYS_NR_PIOS 5
Andreas Bießmann8a16a192011-04-18 04:12:35 +0000111#define CONFIG_SYS_HSDRAMC
112#define CONFIG_MMC
Sven Schnelle8aa96822011-10-21 14:49:25 +0200113#define CONFIG_GENERIC_ATMEL_MCI
114#define CONFIG_GENERIC_MMC
Andreas Bießmann8a16a192011-04-18 04:12:35 +0000115#define CONFIG_ATMEL_SPI
Haavard Skinnemoen14682842008-06-20 10:41:05 +0200116
Andreas Bießmann8a16a192011-04-18 04:12:35 +0000117#define CONFIG_SPI_FLASH
118#define CONFIG_SPI_FLASH_ATMEL
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +0200119
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200120#define CONFIG_SYS_DCACHE_LINESZ 32
121#define CONFIG_SYS_ICACHE_LINESZ 32
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +0200122
123#define CONFIG_NR_DRAM_BANKS 1
124
Andreas Bießmann8a16a192011-04-18 04:12:35 +0000125#define CONFIG_SYS_FLASH_CFI
126#define CONFIG_FLASH_CFI_DRIVER
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +0200127
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200128#define CONFIG_SYS_FLASH_BASE 0x00000000
129#define CONFIG_SYS_FLASH_SIZE 0x800000
130#define CONFIG_SYS_MAX_FLASH_BANKS 1
131#define CONFIG_SYS_MAX_FLASH_SECT 135
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +0200132
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200133#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Andreas Bießmannf2c6d392011-04-18 04:12:43 +0000134#define CONFIG_SYS_TEXT_BASE 0x00000000
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +0200135
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200136#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
137#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
138#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +0200139
Andreas Bießmann8a16a192011-04-18 04:12:35 +0000140#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200141#define CONFIG_ENV_SIZE 65536
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +0200143
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200144#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +0200145
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200146#define CONFIG_SYS_MALLOC_LEN (256*1024)
147#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +0200148
149/* Allow 4MB for the kernel run-time image */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200150#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
151#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +0200152
153/* Other configuration settings that shouldn't have to change all that often */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200154#define CONFIG_SYS_PROMPT "U-Boot> "
155#define CONFIG_SYS_CBSIZE 256
156#define CONFIG_SYS_MAXARGS 16
157#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
Andreas Bießmann8a16a192011-04-18 04:12:35 +0000158#define CONFIG_SYS_LONGHELP
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +0200159
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200160#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
161#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
Haavard Skinnemoen6f08daf2007-11-22 16:51:39 +0100162
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200163#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
Haavard Skinnemoenb62a4312007-04-14 17:11:49 +0200164
165#endif /* __CONFIG_H */