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git01.mediatek.com / filogic / uboot / 8a2b47f199182334308296dfbf7a6261f072069e / . / drivers / clk / sunxi / clk_r40.c
blob: ee1e86d22eb992a02a7f5ad2ef4286ac49ed13f2 [file] [log] [blame]
Jagan Teki66c07fd2018-08-05 11:16:33 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <asm/arch/ccu.h>
12#include <dt-bindings/clock/sun8i-r40-ccu.h>
13#include <dt-bindings/reset/sun8i-r40-ccu.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]14#include <linux/bitops.h>
Jagan Teki66c07fd2018-08-05 11:16:33 +0530[diff] [blame]15
16static struct ccu_clk_gate r40_gates[] = {
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
18 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
19 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
20 [CLK_BUS_MMC3] = GATE(0x060, BIT(11)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]21 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
22 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
23 [CLK_BUS_SPI2] = GATE(0x060, BIT(22)),
24 [CLK_BUS_SPI3] = GATE(0x060, BIT(23)),
Jagan Teki66c07fd2018-08-05 11:16:33 +0530[diff] [blame]25 [CLK_BUS_OTG] = GATE(0x060, BIT(25)),
26 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
27 [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
28 [CLK_BUS_EHCI2] = GATE(0x060, BIT(28)),
29 [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
30 [CLK_BUS_OHCI1] = GATE(0x060, BIT(30)),
31 [CLK_BUS_OHCI2] = GATE(0x060, BIT(31)),
32
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]33 [CLK_BUS_GMAC] = GATE(0x064, BIT(17)),
34
Jagan Teki8cf08ea2018-12-30 21:29:24 +0530[diff] [blame]35 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
36 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
37 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
38 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
39 [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
40 [CLK_BUS_UART5] = GATE(0x06c, BIT(21)),
41 [CLK_BUS_UART6] = GATE(0x06c, BIT(22)),
42 [CLK_BUS_UART7] = GATE(0x06c, BIT(23)),
43
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]44 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
45 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
46 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
47 [CLK_SPI3] = GATE(0x0ac, BIT(31)),
48
Jagan Teki66c07fd2018-08-05 11:16:33 +0530[diff] [blame]49 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
50 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
51 [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
52 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
53 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
54 [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),
55};
56
57static struct ccu_reset r40_resets[] = {
58 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
59 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
60 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
61
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]62 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
63 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
64 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
65 [RST_BUS_MMC3] = RESET(0x2c0, BIT(11)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]66 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
67 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
68 [RST_BUS_SPI2] = RESET(0x2c0, BIT(22)),
69 [RST_BUS_SPI3] = RESET(0x2c0, BIT(23)),
Jagan Teki66c07fd2018-08-05 11:16:33 +0530[diff] [blame]70 [RST_BUS_OTG] = RESET(0x2c0, BIT(25)),
71 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)),
72 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
73 [RST_BUS_EHCI2] = RESET(0x2c0, BIT(28)),
74 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
75 [RST_BUS_OHCI1] = RESET(0x2c0, BIT(30)),
76 [RST_BUS_OHCI2] = RESET(0x2c0, BIT(31)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]77
Jagan Tekifc228202019-04-15 16:42:16 +0530[diff] [blame]78 [RST_BUS_GMAC] = RESET(0x2c4, BIT(17)),
79
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]80 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
81 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
82 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
83 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
84 [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
85 [RST_BUS_UART5] = RESET(0x2d8, BIT(21)),
86 [RST_BUS_UART6] = RESET(0x2d8, BIT(22)),
87 [RST_BUS_UART7] = RESET(0x2d8, BIT(23)),
Jagan Teki66c07fd2018-08-05 11:16:33 +0530[diff] [blame]88};
89
90static const struct ccu_desc r40_ccu_desc = {
91 .gates = r40_gates,
92 .resets = r40_resets,
93};
94
95static int r40_clk_bind(struct udevice *dev)
96{
97 return sunxi_reset_bind(dev, ARRAY_SIZE(r40_resets));
98}
99
100static const struct udevice_id r40_clk_ids[] = {
101 { .compatible = "allwinner,sun8i-r40-ccu",
102 .data = (ulong)&r40_ccu_desc },
103 { }
104};
105
106U_BOOT_DRIVER(clk_sun8i_r40) = {
107 .name = "sun8i_r40_ccu",
108 .id = UCLASS_CLK,
109 .of_match = r40_clk_ids,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700[diff] [blame^]110 .priv_auto = sizeof(struct ccu_priv),
Jagan Teki66c07fd2018-08-05 11:16:33 +0530[diff] [blame]111 .ops = &sunxi_clk_ops,
112 .probe = sunxi_clk_probe,
113 .bind = r40_clk_bind,
114};