| Siew Chin Lim | d9f416f | 2021-08-10 11:26:40 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * U-Boot additions |
| 4 | * |
| 5 | * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> |
| 6 | */ |
| 7 | |
| 8 | #include "socfpga_n5x-u-boot.dtsi" |
| 9 | |
| 10 | /{ |
| 11 | aliases { |
| 12 | spi0 = &qspi; |
| 13 | i2c0 = &i2c1; |
| 14 | }; |
| 15 | |
| 16 | memory { |
| 17 | /* |
| 18 | * Memory type: DDR4 (non-interleaving mode) |
| 19 | * 16GB |
| 20 | * <0 0x00000000 0 0x80000000>, |
| 21 | * <4 0x80000000 3 0x80000000>; |
| 22 | * |
| 23 | * 8GB |
| 24 | * <0 0x00000000 0 0x80000000>, |
| 25 | * <2 0x80000000 1 0x80000000>; |
| 26 | * |
| 27 | * 4GB |
| 28 | * <0 0x00000000 0 0x80000000>, |
| 29 | * <1 0x80000000 0 0x80000000>; |
| 30 | * |
| 31 | * Memory type: LPDDR4 (non-interleaving mode) |
| 32 | * Total memory size 3GB, usable = 2.5GB, 0.5GB trade off for secure |
| 33 | * region. |
| 34 | */ |
| 35 | reg = <0 0x00000000 0 0x60000000>, |
| 36 | <0x10 0x00100000 0 0x40000000>; |
| 37 | }; |
| 38 | }; |
| 39 | |
| 40 | &flash0 { |
| 41 | compatible = "jedec,spi-nor"; |
| 42 | spi-tx-bus-width = <4>; |
| 43 | spi-rx-bus-width = <4>; |
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 44 | bootph-all; |
| Siew Chin Lim | d9f416f | 2021-08-10 11:26:40 +0800 | [diff] [blame] | 45 | }; |
| 46 | |
| 47 | &i2c1 { |
| 48 | status = "okay"; |
| 49 | }; |
| 50 | |
| 51 | &mmc { |
| 52 | drvsel = <3>; |
| 53 | smplsel = <0>; |
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 54 | bootph-all; |
| Siew Chin Lim | d9f416f | 2021-08-10 11:26:40 +0800 | [diff] [blame] | 55 | }; |
| 56 | |
| 57 | &qspi { |
| 58 | status = "okay"; |
| 59 | }; |
| 60 | |
| 61 | &watchdog0 { |
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 62 | bootph-all; |
| Siew Chin Lim | d9f416f | 2021-08-10 11:26:40 +0800 | [diff] [blame] | 63 | }; |