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git01.mediatek.com / filogic / uboot / 89a6593e6fa0e849d4d633e9c060f52ea909604d / . / arch / arm / dts / rk3568-rock-3a-u-boot.dtsi
blob: b05b7151e6c71e96e0a01d8ecc3e373976925463 [file] [log] [blame]
Akash Gajjara01866a2023-02-14 20:48:40 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2021 Rockchip Electronics Co., Ltd
4 * (C) Copyright 2023 Akash Gajjar <gajjar04akash@gmail.com>
5 */
6
7#include "rk356x-u-boot.dtsi"
8
9/ {
10 chosen {
11 stdout-path = &uart2;
Akash Gajjara01866a2023-02-14 20:48:40 +0530[diff] [blame]12 };
13};
14
Jonas Karlman1e1bc892023-07-22 13:30:23 +0000[diff] [blame]15&pcie3x2 {
Jonas Karlmandd7ee8a2023-07-31 04:28:34 +0000[diff] [blame]16 pinctrl-0 = <&pcie3x2_reset_h>;
Jonas Karlman1e1bc892023-07-22 13:30:23 +0000[diff] [blame]17};
18
Jonas Karlmanac46dc72023-05-17 18:26:34 +0000[diff] [blame]19&pinctrl {
Jonas Karlman1e1bc892023-07-22 13:30:23 +0000[diff] [blame]20 pcie {
21 pcie3x2_reset_h: pcie3x2-reset-h {
22 rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
23 };
24 };
Jonas Karlmanac46dc72023-05-17 18:26:34 +0000[diff] [blame]25};
26
Jonas Karlman2cc03212023-04-18 16:46:38 +0000[diff] [blame]27&sdhci {
28 cap-mmc-highspeed;
29 mmc-ddr-1_8v;
30 mmc-hs200-1_8v;
31 mmc-hs400-1_8v;
32 mmc-hs400-enhanced-strobe;
33};
34
Jonas Karlmana9d8d532023-05-17 18:26:35 +0000[diff] [blame]35&sfc {
36 bootph-pre-ram;
37 u-boot,spl-sfc-no-dma;
38 #address-cells = <1>;
39 #size-cells = <0>;
40 status = "okay";
41
42 flash@0 {
43 bootph-pre-ram;
44 compatible = "jedec,spi-nor";
45 reg = <0>;
46 spi-max-frequency = <24000000>;
47 spi-rx-bus-width = <4>;
48 spi-tx-bus-width = <1>;
49 };
50};
51
Akash Gajjara01866a2023-02-14 20:48:40 +0530[diff] [blame]52&uart2 {
53 clock-frequency = <24000000>;
Tom Rinide70b472023-03-27 15:20:19 -0400[diff] [blame]54 bootph-all;
Akash Gajjara01866a2023-02-14 20:48:40 +0530[diff] [blame]55 status = "okay";
56};