| Vikas Manocha | e8bb551 | 2015-07-02 18:29:46 -0700 | [diff] [blame] | 1 | Cadence QSPI controller device tree bindings |
| 2 | -------------------------------------------- |
| 3 | |
| 4 | Required properties: |
| 5 | - compatible : should be "cadence,qspi". |
| 6 | - reg : 1.Physical base address and size of SPI registers map. |
| 7 | 2. Physical base address & size of NOR Flash. |
| 8 | - clocks : Clock phandles (see clock bindings for details). |
| 9 | - sram-size : spi controller sram size. |
| 10 | - status : enable in requried dts. |
| 11 | |
| 12 | connected flash properties |
| 13 | -------------------------- |
| 14 | |
| 15 | - spi-max-frequency : Max supported spi frequency. |
| 16 | - page-size : Flash page size. |
| 17 | - block-size : Flash memory block size. |
| 18 | - tshsl-ns : Added delay in master reference clocks (ref_clk) for |
| 19 | the length that the master mode chip select outputs |
| 20 | are de-asserted between transactions. |
| 21 | - tsd2d-ns : Delay in master reference clocks (ref_clk) between one |
| 22 | chip select being de-activated and the activation of |
| 23 | another. |
| 24 | - tchsh-ns : Delay in master reference clocks between last bit of |
| 25 | current transaction and de-asserting the device chip |
| 26 | select (n_ss_out). |
| 27 | - tslch-ns : Delay in master reference clocks between setting |
| 28 | n_ss_out low and first bit transfer |