wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2000 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <asm/processor.h> |
Stefan Roese | 247e9d7 | 2010-09-09 19:18:00 +0200 | [diff] [blame] | 10 | #include <asm/ppc4xx-i2c.h> |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 11 | #include <command.h> |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 12 | #include <rtc.h> |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 13 | #include <post.h> |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 14 | #include <net.h> |
| 15 | #include <malloc.h> |
| 16 | |
| 17 | #define L1_MEMSIZE (32*1024*1024) |
| 18 | |
| 19 | /* the std. DHCP stufff */ |
| 20 | #define DHCP_ROUTER 3 |
| 21 | #define DHCP_NETMASK 1 |
| 22 | #define DHCP_BOOTFILE 67 |
| 23 | #define DHCP_ROOTPATH 17 |
| 24 | #define DHCP_HOSTNAME 12 |
| 25 | |
| 26 | /* some extras used by CRAY |
| 27 | * |
| 28 | * on the server this looks like: |
| 29 | * |
| 30 | * option L1-initrd-image code 224 = string; |
| 31 | * option L1-initrd-image "/opt/craysv2/craymcu/l1/flash/initrd.image" |
| 32 | */ |
| 33 | #define DHCP_L1_INITRD 224 |
| 34 | |
| 35 | /* new, [better?] way via official vendor-extensions, defining an option |
| 36 | * space. |
| 37 | * on the server this looks like: |
| 38 | * |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 39 | * option space CRAYL1; |
| 40 | * option CRAYL1.initrd code 3 = string; |
| 41 | * ..etc... |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 42 | */ |
| 43 | #define DHCP_VENDOR_SPECX 43 |
| 44 | #define DHCP_VX_INITRD 3 |
| 45 | #define DHCP_VX_BOOTCMD 4 |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 46 | #define DHCP_VX_BOOTARGS 5 |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 47 | #define DHCP_VX_ROOTDEV 6 |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 48 | #define DHCP_VX_FROMFLASH 7 |
| 49 | #define DHCP_VX_BOOTSCRIPT 8 |
| 50 | #define DHCP_VX_RCFILE 9 |
| 51 | #define DHCP_VX_MAGIC 10 |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 52 | |
| 53 | /* Things DHCP server can tellme about. If there's no flash address, then |
| 54 | * they dont participate in 'update' to flash, and we force their values |
| 55 | * back to '0' every boot to be sure to get them fresh from DHCP. Yes, I |
| 56 | * know this is a pain... |
| 57 | * |
| 58 | * If I get no bootfile, boot from flash. If rootpath, use that. If no |
| 59 | * rootpath use initrd in flash. |
| 60 | */ |
| 61 | typedef struct dhcp_item_s { |
| 62 | u8 dhcp_option; |
| 63 | u8 dhcp_vendor_option; |
| 64 | char *dhcpvalue; |
| 65 | char *envname; |
| 66 | } dhcp_item_t; |
| 67 | static dhcp_item_t Things[] = { |
| 68 | {DHCP_ROUTER, 0, NULL, "gateway"}, |
| 69 | {DHCP_NETMASK, 0, NULL, "netmask"}, |
| 70 | {DHCP_BOOTFILE, 0, NULL, "bootfile"}, |
| 71 | {DHCP_ROOTPATH, 0, NULL, "rootpath"}, |
| 72 | {DHCP_HOSTNAME, 0, NULL, "hostname"}, |
| 73 | {DHCP_L1_INITRD, 0, NULL, "initrd"}, |
| 74 | /* and the other way.. */ |
| 75 | {DHCP_VENDOR_SPECX, DHCP_VX_INITRD, NULL, "initrd"}, |
| 76 | {DHCP_VENDOR_SPECX, DHCP_VX_BOOTCMD, NULL, "bootcmd"}, |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 77 | {DHCP_VENDOR_SPECX, DHCP_VX_FROMFLASH, NULL, "fromflash"}, |
| 78 | {DHCP_VENDOR_SPECX, DHCP_VX_BOOTSCRIPT, NULL, "bootscript"}, |
| 79 | {DHCP_VENDOR_SPECX, DHCP_VX_RCFILE, NULL, "rcfile"}, |
| 80 | {DHCP_VENDOR_SPECX, DHCP_VX_BOOTARGS, NULL, "xbootargs"}, |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 81 | {DHCP_VENDOR_SPECX, DHCP_VX_ROOTDEV, NULL, NULL}, |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 82 | {DHCP_VENDOR_SPECX, DHCP_VX_MAGIC, NULL, NULL} |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 83 | }; |
| 84 | |
| 85 | #define N_THINGS ((sizeof(Things))/(sizeof(dhcp_item_t))) |
| 86 | |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 87 | extern char bootscript[]; |
| 88 | |
| 89 | /* Here is the boot logic as HUSH script. Overridden by any TFP provided |
| 90 | * bootscript file. |
| 91 | */ |
| 92 | |
| 93 | static void init_sdram (void); |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 94 | |
| 95 | /* ------------------------------------------------------------------------- */ |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 96 | int board_early_init_f (void) |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 97 | { |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 98 | /* Running from ROM: global data is still READONLY */ |
| 99 | init_sdram (); |
Stefan Roese | 707fd36 | 2009-09-24 09:55:50 +0200 | [diff] [blame] | 100 | mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
| 101 | mtdcr (UIC0ER, 0x00000000); /* disable all ints */ |
| 102 | mtdcr (UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */ |
| 103 | mtdcr (UIC0PR, 0xFFFFFFE0); /* set int polarities */ |
| 104 | mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ |
| 105 | mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ |
| 106 | mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 107 | return 0; |
| 108 | } |
| 109 | |
| 110 | /* ------------------------------------------------------------------------- */ |
| 111 | int checkboard (void) |
| 112 | { |
| 113 | return (0); |
| 114 | } |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 115 | /* ------------------------------------------------------------------------- */ |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 116 | |
| 117 | /* ------------------------------------------------------------------------- */ |
| 118 | int misc_init_r (void) |
| 119 | { |
Wolfgang Denk | 7fb5266 | 2005-10-13 16:45:02 +0200 | [diff] [blame] | 120 | char *s, *e; |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 121 | image_header_t *hdr; |
| 122 | time_t timestamp; |
| 123 | struct rtc_time tm; |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 124 | char bootcmd[32]; |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 125 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 126 | hdr = (image_header_t *) (CONFIG_SYS_MONITOR_BASE - image_get_header_size ()); |
Marian Balakowicz | dbdd16a | 2008-02-04 08:28:09 +0100 | [diff] [blame] | 127 | #if defined(CONFIG_FIT) |
Marian Balakowicz | d7c88a4 | 2008-02-29 14:58:34 +0100 | [diff] [blame] | 128 | if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { |
Marian Balakowicz | dbdd16a | 2008-02-04 08:28:09 +0100 | [diff] [blame] | 129 | puts ("Non legacy image format not supported\n"); |
| 130 | return -1; |
| 131 | } |
| 132 | #endif |
| 133 | |
Marian Balakowicz | 41d71ed | 2008-01-08 18:14:09 +0100 | [diff] [blame] | 134 | timestamp = (time_t)image_get_time (hdr); |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 135 | to_tm (timestamp, &tm); |
| 136 | printf ("Welcome to U-Boot on Cray L1. Compiled %4d-%02d-%02d %2d:%02d:%02d (UTC)\n", tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec); |
| 137 | |
| 138 | #define FACTORY_SETTINGS 0xFFFC0000 |
| 139 | if ((s = getenv ("ethaddr")) == NULL) { |
Wolfgang Denk | 7fb5266 | 2005-10-13 16:45:02 +0200 | [diff] [blame] | 140 | e = (char *) (FACTORY_SETTINGS); |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 141 | if (*(e + 0) != '0' |
| 142 | || *(e + 1) != '0' |
| 143 | || *(e + 2) != ':' |
| 144 | || *(e + 3) != '4' || *(e + 4) != '0' || *(e + 17) != '\0') { |
| 145 | printf ("No valid MAC address in flash location 0x3C0000!\n"); |
| 146 | } else { |
| 147 | printf ("Factory MAC: %s\n", e); |
| 148 | setenv ("ethaddr", e); |
| 149 | } |
| 150 | } |
Wolfgang Denk | 85c25df | 2009-04-01 23:34:12 +0200 | [diff] [blame] | 151 | sprintf (bootcmd,"source %X",(unsigned)bootscript); |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 152 | setenv ("bootcmd", bootcmd); |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 153 | return (0); |
| 154 | } |
| 155 | |
| 156 | /* ------------------------------------------------------------------------- */ |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 157 | /* stubs so we can print dates w/o any nvram RTC.*/ |
Yuri Tikhonov | 9bacd94 | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 158 | int rtc_get (struct rtc_time *tmp) |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 159 | { |
Yuri Tikhonov | 9bacd94 | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 160 | return 0; |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 161 | } |
Jean-Christophe PLAGNIOL-VILLARD | 97a2e10 | 2008-09-01 23:06:23 +0200 | [diff] [blame] | 162 | int rtc_set (struct rtc_time *tmp) |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 163 | { |
Jean-Christophe PLAGNIOL-VILLARD | 97a2e10 | 2008-09-01 23:06:23 +0200 | [diff] [blame] | 164 | return 0; |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 165 | } |
| 166 | void rtc_reset (void) |
| 167 | { |
| 168 | return; |
| 169 | } |
| 170 | |
| 171 | /* ------------------------------------------------------------------------- */ |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 172 | /* Do sdram bank init in C so I can read it..no console to print to yet! |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 173 | */ |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 174 | static void init_sdram (void) |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 175 | { |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 176 | unsigned long tmp; |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 177 | |
| 178 | /* write SDRAM bank 0 register */ |
Stefan Roese | 6987e65 | 2009-09-24 13:59:57 +0200 | [diff] [blame] | 179 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 180 | mtdcr (SDRAM0_CFGDATA, 0x00062001); |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 181 | |
| 182 | /* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */ |
| 183 | /* To set the appropriate timings, we need to know the SDRAM speed. */ |
| 184 | /* We can use the PLB speed since the SDRAM speed is the same as */ |
| 185 | /* the PLB speed. The PLB speed is the FBK divider times the */ |
Wolfgang Denk | af0501a | 2008-10-19 02:35:50 +0200 | [diff] [blame] | 186 | /* 405GP reference clock, which on the L1 is 25MHz. */ |
| 187 | /* Thus, if FBK div is 2, SDRAM is 50MHz; if FBK div is 3, SDRAM is */ |
| 188 | /* 150MHz; if FBK is 3, SDRAM is 150MHz. */ |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 189 | |
| 190 | /* divisor = ((mfdcr(strap)>> 28) & 0x3); */ |
| 191 | |
Wolfgang Denk | af0501a | 2008-10-19 02:35:50 +0200 | [diff] [blame] | 192 | /* write SDRAM timing for 100MHz. */ |
Stefan Roese | 6987e65 | 2009-09-24 13:59:57 +0200 | [diff] [blame] | 193 | mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 194 | mtdcr (SDRAM0_CFGDATA, 0x0086400D); |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 195 | |
| 196 | /* write SDRAM refresh interval register */ |
Stefan Roese | 6987e65 | 2009-09-24 13:59:57 +0200 | [diff] [blame] | 197 | mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 198 | mtdcr (SDRAM0_CFGDATA, 0x05F00000); |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 199 | udelay (200); |
| 200 | |
| 201 | /* sdram controller.*/ |
Stefan Roese | 6987e65 | 2009-09-24 13:59:57 +0200 | [diff] [blame] | 202 | mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 203 | mtdcr (SDRAM0_CFGDATA, 0x90800000); |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 204 | udelay (200); |
| 205 | |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 206 | /* initially, disable ECC on all banks */ |
| 207 | udelay (200); |
Stefan Roese | 6987e65 | 2009-09-24 13:59:57 +0200 | [diff] [blame] | 208 | mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 209 | tmp = mfdcr (SDRAM0_CFGDATA); |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 210 | tmp &= 0xff0fffff; |
Stefan Roese | 6987e65 | 2009-09-24 13:59:57 +0200 | [diff] [blame] | 211 | mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 212 | mtdcr (SDRAM0_CFGDATA, tmp); |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 213 | |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 214 | return; |
| 215 | } |
| 216 | |
| 217 | extern int memory_post_test (int flags); |
| 218 | |
| 219 | int testdram (void) |
| 220 | { |
| 221 | unsigned long tmp; |
| 222 | uint *pstart = (uint *) 0x00000000; |
| 223 | uint *pend = (uint *) L1_MEMSIZE; |
| 224 | uint *p; |
| 225 | |
Wolfgang Denk | 76af278 | 2010-07-24 21:55:43 +0200 | [diff] [blame] | 226 | if (getenv_f("booted",NULL,0) <= 0) |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 227 | { |
| 228 | printf ("testdram.."); |
| 229 | /*AA*/ |
| 230 | for (p = pstart; p < pend; p++) |
| 231 | *p = 0xaaaaaaaa; |
| 232 | for (p = pstart; p < pend; p++) { |
| 233 | if (*p != 0xaaaaaaaa) { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 234 | printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 235 | (uint) p, *p, 0xaaaaaaaa); |
| 236 | return 1; |
| 237 | } |
| 238 | } |
| 239 | /*55*/ |
| 240 | for (p = pstart; p < pend; p++) |
| 241 | *p = 0x55555555; |
| 242 | for (p = pstart; p < pend; p++) { |
| 243 | if (*p != 0x55555555) { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 244 | printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 245 | (uint) p, *p, 0x55555555); |
| 246 | return 1; |
| 247 | } |
| 248 | } |
| 249 | /*addr*/ |
| 250 | for (p = pstart; p < pend; p++) |
| 251 | *p = (unsigned)p; |
| 252 | for (p = pstart; p < pend; p++) { |
| 253 | if (*p != (unsigned)p) { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 254 | printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 255 | (uint) p, *p, (uint)p); |
| 256 | return 1; |
| 257 | } |
| 258 | } |
| 259 | printf ("Success. "); |
| 260 | } |
| 261 | printf ("Enable ECC.."); |
| 262 | |
Stefan Roese | 6987e65 | 2009-09-24 13:59:57 +0200 | [diff] [blame] | 263 | mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 264 | tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000; |
Stefan Roese | 6987e65 | 2009-09-24 13:59:57 +0200 | [diff] [blame] | 265 | mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 266 | mtdcr (SDRAM0_CFGDATA, tmp); |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 267 | udelay (600); |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 268 | for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L) |
| 269 | ; |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 270 | udelay (400); |
Stefan Roese | 6987e65 | 2009-09-24 13:59:57 +0200 | [diff] [blame] | 271 | mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 272 | tmp = mfdcr (SDRAM0_CFGDATA); |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 273 | tmp |= 0x00800000; |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 274 | mtdcr (SDRAM0_CFGDATA, tmp); |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 275 | udelay (400); |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 276 | printf ("enabled.\n"); |
| 277 | return (0); |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 278 | } |
| 279 | |
| 280 | /* ------------------------------------------------------------------------- */ |
| 281 | static u8 *dhcp_env_update (u8 thing, u8 * pop) |
| 282 | { |
| 283 | u8 i, oplen; |
| 284 | |
| 285 | oplen = *(pop + 1); |
| 286 | |
| 287 | if ((Things[thing].dhcpvalue = malloc (oplen)) == NULL) { |
| 288 | printf ("Whoops! failed to malloc space for DHCP thing %s\n", |
| 289 | Things[thing].envname); |
| 290 | return NULL; |
| 291 | } |
| 292 | for (i = 0; (i < oplen); i++) |
| 293 | if ((*(Things[thing].dhcpvalue + i) = *(pop + 2 + i)) == ' ') |
| 294 | break; |
| 295 | *(Things[thing].dhcpvalue + i) = '\0'; |
| 296 | |
| 297 | /* set env. */ |
| 298 | if (Things[thing].envname) |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 299 | { |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 300 | setenv (Things[thing].envname, Things[thing].dhcpvalue); |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 301 | } |
Wolfgang Denk | 7fb5266 | 2005-10-13 16:45:02 +0200 | [diff] [blame] | 302 | return ((u8 *)(Things[thing].dhcpvalue)); |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 303 | } |
| 304 | |
| 305 | /* ------------------------------------------------------------------------- */ |
| 306 | u8 *dhcp_vendorex_prep (u8 * e) |
| 307 | { |
| 308 | u8 thing; |
| 309 | |
| 310 | /* ask for the things I want. */ |
| 311 | *e++ = 55; /* Parameter Request List */ |
| 312 | *e++ = N_THINGS; |
| 313 | for (thing = 0; thing < N_THINGS; thing++) |
| 314 | *e++ = Things[thing].dhcp_option; |
| 315 | *e++ = 255; |
| 316 | |
| 317 | return e; |
| 318 | } |
| 319 | |
| 320 | /* ------------------------------------------------------------------------- */ |
| 321 | /* .. return NULL means it wasnt mine, non-null means I got it..*/ |
| 322 | u8 *dhcp_vendorex_proc (u8 * pop) |
| 323 | { |
| 324 | u8 oplen, *sub_op, sub_oplen, *retval; |
| 325 | u8 thing = 0; |
| 326 | |
| 327 | retval = NULL; |
| 328 | oplen = *(pop + 1); |
| 329 | /* if pop is vender spec indicator, there are sub-options. */ |
| 330 | if (*pop == DHCP_VENDOR_SPECX) { |
| 331 | for (sub_op = pop + 2; |
| 332 | oplen && (sub_oplen = *(sub_op + 1)); |
| 333 | oplen -= sub_oplen, sub_op += (sub_oplen + 2)) { |
| 334 | for (thing = 0; thing < N_THINGS; thing++) { |
| 335 | if (*sub_op == Things[thing].dhcp_vendor_option) { |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 336 | if (!(retval = dhcp_env_update (thing, sub_op))) { |
| 337 | return NULL; |
| 338 | } |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 339 | } |
| 340 | } |
| 341 | } |
| 342 | } else { |
| 343 | for (thing = 0; thing < N_THINGS; thing++) { |
| 344 | if (*pop == Things[thing].dhcp_option) |
| 345 | if (!(retval = dhcp_env_update (thing, pop))) |
| 346 | return NULL; |
| 347 | } |
| 348 | } |
wdenk | 0893c47 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 349 | return (pop); |
wdenk | 47d1a6e | 2002-11-03 00:01:44 +0000 | [diff] [blame] | 350 | } |