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git01.mediatek.com / filogic / uboot / 88fd156ec4d59c689b1061c0c0dbde5e32551daf / . / arch / arm / dts / am335x-boneblack.dts
blob: b956e2f60fe0701bf35ccac55d0388017dc41a10 [file] [log] [blame]
Paul Barkera27d9f62021-07-12 21:14:09 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]2/*
Paul Barkera27d9f62021-07-12 21:14:09 +0100[diff] [blame]3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]4 */
5/dts-v1/;
6
7#include "am33xx.dtsi"
8#include "am335x-bone-common.dtsi"
Paul Barkera27d9f62021-07-12 21:14:09 +0100[diff] [blame]9#include "am335x-boneblack-common.dtsi"
Paul Barker273f51d2022-04-11 15:41:59 +0000[diff] [blame]10#include "am335x-boneblack-hdmi.dtsi"
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]11
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]12/ {
13 model = "TI AM335x BeagleBone Black";
14 compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]15};
16
Paul Barkera27d9f62021-07-12 21:14:09 +0100[diff] [blame]17&cpu0_opp_table {
18 /*
19 * All PG 2.0 silicon may not support 1GHz but some of the early
20 * BeagleBone Blacks have PG 2.0 silicon which is guaranteed
21 * to support 1GHz OPP so enable it for PG 2.0 on this board.
22 */
23 oppnitro-1000000000 {
24 opp-supported-hw = <0x06 0x0100>;
25 };
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]26};
27
Paul Barkera27d9f62021-07-12 21:14:09 +0100[diff] [blame]28&gpio0 {
29 gpio-line-names =
30 "[mdio_data]",
31 "[mdio_clk]",
32 "P9_22 [spi0_sclk]",
33 "P9_21 [spi0_d0]",
34 "P9_18 [spi0_d1]",
35 "P9_17 [spi0_cs0]",
36 "[mmc0_cd]",
37 "P8_42A [ecappwm0]",
38 "P8_35 [lcd d12]",
39 "P8_33 [lcd d13]",
40 "P8_31 [lcd d14]",
41 "P8_32 [lcd d15]",
42 "P9_20 [i2c2_sda]",
43 "P9_19 [i2c2_scl]",
44 "P9_26 [uart1_rxd]",
45 "P9_24 [uart1_txd]",
46 "[rmii1_txd3]",
47 "[rmii1_txd2]",
48 "[usb0_drvvbus]",
49 "[hdmi cec]",
50 "P9_41B",
51 "[rmii1_txd1]",
52 "P8_19 [ehrpwm2a]",
53 "P8_13 [ehrpwm2b]",
54 "NC",
55 "NC",
56 "P8_14",
57 "P8_17",
58 "[rmii1_txd0]",
59 "[rmii1_refclk]",
60 "P9_11 [uart4_rxd]",
61 "P9_13 [uart4_txd]";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]62};
63
Paul Barkera27d9f62021-07-12 21:14:09 +0100[diff] [blame]64&gpio1 {
65 gpio-line-names =
66 "P8_25 [mmc1_dat0]",
67 "[mmc1_dat1]",
68 "P8_5 [mmc1_dat2]",
69 "P8_6 [mmc1_dat3]",
70 "P8_23 [mmc1_dat4]",
71 "P8_22 [mmc1_dat5]",
72 "P8_3 [mmc1_dat6]",
73 "P8_4 [mmc1_dat7]",
74 "NC",
75 "NC",
76 "NC",
77 "NC",
78 "P8_12",
79 "P8_11",
80 "P8_16",
81 "P8_15",
82 "P9_15A",
83 "P9_23",
84 "P9_14 [ehrpwm1a]",
85 "P9_16 [ehrpwm1b]",
86 "[emmc rst]",
87 "[usr0 led]",
88 "[usr1 led]",
89 "[usr2 led]",
90 "[usr3 led]",
91 "[hdmi irq]",
92 "[usb vbus oc]",
93 "[hdmi audio]",
94 "P9_12",
95 "P8_26",
96 "P8_21 [emmc]",
97 "P8_20 [emmc]";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]98};
99
Paul Barkera27d9f62021-07-12 21:14:09 +0100[diff] [blame]100&gpio2 {
101 gpio-line-names =
102 "P9_15B",
103 "P8_18",
104 "P8_7",
105 "P8_8",
106 "P8_10",
107 "P8_9",
108 "P8_45 [hdmi]",
109 "P8_46 [hdmi]",
110 "P8_43 [hdmi]",
111 "P8_44 [hdmi]",
112 "P8_41 [hdmi]",
113 "P8_42 [hdmi]",
114 "P8_39 [hdmi]",
115 "P8_40 [hdmi]",
116 "P8_37 [hdmi]",
117 "P8_38 [hdmi]",
118 "P8_36 [hdmi]",
119 "P8_34 [hdmi]",
120 "[rmii1_rxd3]",
121 "[rmii1_rxd2]",
122 "[rmii1_rxd1]",
123 "[rmii1_rxd0]",
124 "P8_27 [hdmi]",
125 "P8_29 [hdmi]",
126 "P8_28 [hdmi]",
127 "P8_30 [hdmi]",
128 "[mmc0_dat3]",
129 "[mmc0_dat2]",
130 "[mmc0_dat1]",
131 "[mmc0_dat0]",
132 "[mmc0_clk]",
133 "[mmc0_cmd]";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]134};
135
Paul Barkera27d9f62021-07-12 21:14:09 +0100[diff] [blame]136&gpio3 {
137 gpio-line-names =
138 "[mii col]",
139 "[mii crs]",
140 "[mii rx err]",
141 "[mii tx en]",
142 "[mii rx dv]",
143 "[i2c0 sda]",
144 "[i2c0 scl]",
145 "[jtag emu0]",
146 "[jtag emu1]",
147 "[mii tx clk]",
148 "[mii rx clk]",
149 "NC",
150 "NC",
151 "[usb vbus en]",
152 "P9_31 [spi1_sclk]",
153 "P9_29 [spi1_d0]",
154 "P9_30 [spi1_d1]",
155 "P9_28 [spi1_cs0]",
156 "P9_42B [ecappwm0]",
157 "P9_27",
158 "P9_41A",
159 "P9_25",
160 "NC",
161 "NC",
162 "NC",
163 "NC",
164 "NC",
165 "NC",
166 "NC",
167 "NC",
168 "NC",
169 "NC";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]170};
Andrew Davisa45320d2023-04-11 13:25:05 -0500[diff] [blame]171
172&baseboard_eeprom {
173 vcc-supply = <&ldo4_reg>;
174};